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CS42L51
Low Power, Stereo CODEC with Headphone Amp
DIGITAL to ANALOG FEATURES
! 98 dB Dynamic Range (A-wtd) ! -86 dB THD+N ! Headphone Amplifier - GND Centered
ANALOG to DIGITAL FEATURES
! 98 dB Dynamic Range (A-wtd) !
-88 dB THD+N - - +32 dB or +16 dB MIC Pre-Amplifiers Analog Programmable Gain Amplifier (PGA)
! Analog Gain Controls
- - - - - - - - -
!
On-Chip Charge Pump Provides -VA_HP No DC-Blocking Capacitor Required 46 mW Power Into Stereo 16 @ 1.8 V 88 mW Power Into Stereo 16 @ 2.5 V -75 dB THD+N Bass & Treble Tone Control, De-Emphasis PCM + ADC Mix w/Independent Vol Control Master Digital Volume Control Soft Ramp & Zero Cross Transitions
! +20 dB Digital Boost ! Programmable Automatic Level Control (ALC)
! Digital Signal Processing Engine
- -
Noise Gate for Noise Suppression Programmable Threshold and Attack/Release Rates
! Independent Channel Control ! Digital Volume Control ! High-Pass Filter Disable for DC Measurements ! Stereo 3:1 Analog Input MUX ! Dual MIC Inputs
Beep Generator - Tone Selections Across Two Octaves - Separate Volume Control - Programmable On & Off Time Intervals - Continuous, Periodic or One-Shot Beep Selections
- -
! Programmable Peak-Detect and Limiter ! Pop and Click Suppression
Programmable, Low Noise MIC Bias Levels Differential MIC Mix for Common Mode Noise Rejection
! Very Low 64 Fs Oversampling Clock Reduces
Power Consumption
1.8 V to 2.5 V
MUX
1.8 V to 3.3 V
1.8 V to 2.5 V
1.8 V to 2.5 V Headphone Amp - GND Centered Headphone Amp - GND Centered Charge Pump
Serial Audio Input Hardware Mode or I2C & SPI Software Mode Control Data
Beep Generator
Digital Signal Processing Engine
MUX
Multibit Modulator
Switched Capacitor DAC and Filter Switched Capacitor DAC and Filter
Left HP Out
Right HP Out
PCM Serial Interface
Level Translator
ALC
Multibit Oversampling ADC Multibit Oversampling ADC
MUX
Reset
PGA MUX
+32 dB
Stereo Input 1 Stereo Input 2 Stereo Input 3 / Mic Input 1 & 2
+32 dB
Serial Audio Output
High Pass Filters
Volume Controls
MUX
PGA
Register Configuration
ALC
MIC Bias
Advance Product Information
http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2005 (All Rights Reserved)
SEPTEMBER '05 DS679A2
CS42L51
SYSTEM FEATURES
! 24-bit Converters ! 4 kHz to 96 kHz Sample Rate ! Multi-bit Delta Sigma Architecture ! Low Power Operation
GENERAL DESCRIPTION
The CS42L51 is a highly integrated, 24-bit, 96 kHz, low power stereo CODEC. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment between 4 kHz and 96 kHz. Both the ADC and DAC offer many features suitable for low power, portable system applications. The ADC input path allows independent channel control of a number of features. An input multiplexer selects between line-level or microphone level inputs for each channel. The microphone input path includes a selectable programmable-gain pre-amplifier stage and a low noise MIC bias voltage supply. A PGA is available for line or microphone inputs and provides analog gain with soft ramp and zero cross transitions. The ADC also features a digital volume attenuator with soft ramp transitions. A programmable ALC and Noise Gate monitor the input signals and adjust the volume levels appropriately. The DAC output path includes a digital signal processing engine. Tone Control provides bass and treble adjustment of four selectable corner frequencies. The Mixer allows independent volume control for both the ADC mix and the PCM mix, as well as a master digital volume control for the analog output. All volume level changes may be configured to occur on soft ramp and zero cross transitions. The DAC also includes de-emphasis, limiting functions and a beep generator delivering tones selectable across a range of two full octaves. The stereo headphone amplifier is powered from a separate positive supply and the integrated charge pump provides a negative supply. This allows a ground-centered analog output with a wide signal swing and eliminates external DC-blocking capacitors. In addition to its many features, the CS42L51 operates from a low-voltage analog and digital core, making this CODEC ideal for portable systems that require extremely low power consumption in a minimal amount of space. The CS42L51 is available in a 32-pin QFN package in both Commercial (-10 to +70 C) and Automotive grades (-40 to +85 C). The CDB42L51 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see "Ordering Information" on page 81 for complete details.
- -
Stereo Playback: 12.93 mW @ 1.8 V Stereo Record and Playback: 20.18 mW @ 1.8 V 1.8 V to 2.5 V Digital & Analog 1.8 V to 3.3 V Interface Logic ADC, DAC, CODEC, MIC Pre-Amplifier, PGA
! Variable Power Supplies
- - -
! Power Down Management
! Software Mode (IC & SPITM Control) ! Hardware Mode (Stand-Alone Control) ! Digital Routing/Mixes:
- - - - - -
Analog Out = ADC + Digital In Digital Out = ADC + Digital In Internal Digital Loopback Mono Mixes Master or Slave Operation High-Impedance Digital Output Option (for easy MUXing between CODEC and Other Data Sources) Quarter-Speed Mode - (i.e. Allows 8 kHz Fs while maintaining a flat noise floor up to 16 kHz)
! Flexible Clocking Options
-
APPLICATIONS
! HDD & Flash-Based Portable Audio Players ! MD Players/Recorders ! PDAs ! Personal Media Players ! Portable Game Consoles ! Digital Voice Recorders ! Digital Camcorders ! Digital Cameras ! Smart Phones 2
DS679A2
CS42L51
TABLE OF CONTENTS
1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................... 7 1.1 Digital I/O Pin Characteristics ............................................................................................ 9 2. TYPICAL CONNECTION DIAGRAMS ................................................................................... 10 3. CHARACTERISTIC AND SPECIFICATION TABLES ........................................................... 12 SPECIFIED OPERATING CONDITIONS ............................................................................... 12 ABSOLUTE MAXIMUM RATINGS ......................................................................................... 12 ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ)............................................ 13 ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) ............................................ 14 ADC DIGITAL FILTER CHARACTERISTICS......................................................................... 15 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ)........................................ 16 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) ........................................ 17 LINE OUTPUT VOLTAGE CHARACTERISTICS ................................................................... 18 HEADPHONE OUTPUT POWER CHARACTERISTICS........................................................ 19 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE................ 20 SWITCHING SPECIFICATIONS - SERIAL PORT ................................................................. 20 SWITCHING SPECIFICATIONS - IC CONTROL PORT....................................................... 22 SWITCHING CHARACTERISTICS - SPI CONTROL PORT.................................................. 23 DC ELECTRICAL CHARACTERISTICS ................................................................................ 24 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ....................................... 24 POWER CONSUMPTION ...................................................................................................... 25 4. APPLICATIONS ..................................................................................................................... 26 4.1 Overview .......................................................................................................................... 26 4.1.1 Architecture ......................................................................................................... 26 4.1.2 Line & MIC Inputs ............................................................................................... 26 4.1.3 Line & Headphone Outputs ................................................................................. 26 4.1.4 Signal Processing Engine ................................................................................... 26 4.1.5 Beep Generator .................................................................................................. 26 4.1.6 Device Control (Hardware or Software Mode) .................................................... 26 4.1.7 Power Management ............................................................................................ 26 4.2 Hardware Mode ............................................................................................................... 27 4.3 Analog Inputs .................................................................................................................. 28 4.3.1 Digital Code, Offset & DC Measurement ............................................................ 28 4.3.2 High-Pass Filter and DC Offset Calibration ........................................................ 29 4.3.3 Digital Routing ..................................................................................................... 29 4.3.4 Differential Inputs ................................................................................................ 29 4.3.4.1 External Passive Components ................................................................ 29 4.3.5 Analog Input Multiplexer ..................................................................................... 30 4.3.6 MIC & PGA Gain ................................................................................................. 31 4.3.7 Automatic Level Control (ALC) ........................................................................... 31 4.3.8 Noise Gate .......................................................................................................... 32 4.4 Analog Outputs ................................................................................................................ 33 4.4.1 De-Emphasis Filter ............................................................................................. 33 4.4.2 Volume Controls ................................................................................................. 34 4.4.3 Mono Channel Mixer ........................................................................................... 34 4.4.4 Beep Generator .................................................................................................. 34 4.4.5 Tone Control ....................................................................................................... 35 4.4.6 Limiter ................................................................................................................. 35 4.4.7 Line-Level Outputs and Filtering ......................................................................... 36 4.4.8 On-Chip Charge Pump ....................................................................................... 36 4.5 Serial Port Clocking ......................................................................................................... 37 4.5.1 Slave ................................................................................................................... 37 4.5.2 Master ................................................................................................................. 38 DS679A2 3
CS42L51
4.5.3 High-Impedance Digital Output ........................................................................... 38 4.5.4 Quarter- and Half-Speed Mode ........................................................................... 39 4.6 Digital Interface Formats ................................................................................................. 39 4.7 Initialization ...................................................................................................................... 40 4.8 Recommended Power-Up Sequence .............................................................................. 40 4.9 Recommended Power-Down Sequence ......................................................................... 41 4.10 Software Mode .............................................................................................................. 42 4.10.1 SPI Control ........................................................................................................ 42 4.10.2 IC Control ......................................................................................................... 42 4.10.3 Memory Address Pointer (MAP) ....................................................................... 44 4.10.3.1 Map Increment (INCR) .......................................................................... 44 REGISTER QUICK REFERENCE .......................................................................................... 45 REGISTER DESCRIPTION .................................................................................................... 47 6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ........................................... 47 6.2 Power Control 1 (Address 02h) ....................................................................................... 47 6.3 MIC Power Control & Speed Control (Address 03h) ...................................................... 48 6.4 Interface Control (Address 04h) ...................................................................................... 49 6.5 MIC Control (Address 05h) .............................................................................................. 51 6.6 ADC Control (Address 06h) ............................................................................................. 52 6.7 ADCx Input Select, Invert & Mute (Address 07h) ............................................................ 53 6.8 DAC Output Control (Address 08h) ................................................................................. 54 6.9 DAC Control (Address 09h) ............................................................................................. 55 6.10 ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh) ..................................... 56 6.11 ADCx Attenuator: ADCA (Address 0Ch) & ADCB (Address 0Dh) ............................................................ 57 6.12 ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh) ............................................................. 58 6.13 PCMX Mixer Volume Control: PCMA (Address 10h) & PCMB (Address 11h) ............................................................. 59 6.14 Beep Frequency & Timing Configuration (Address 12h) ............................................... 60 6.15 Beep Off Time & Volume (Address 13h) ....................................................................... 61 6.16 Beep Configuration & Tone Configuration (Address 14h) ............................................. 62 6.17 Tone Control (Address 15h) .......................................................................................... 63 6.18 AOUTx Volume Control: AOUTA (Address 16h) & AOUTB (Address 17h) ......................................................... 64 6.20 Limiter Threshold SZC Disable (Address 19h) .............................................................. 65 6.21 Limiter Release Rate Register (Address 1Ah) ............................................................... 66 6.22 Limiter Attack Rate Register (Address 1Bh) .................................................................. 67 6.23 ALC Enable & Attack Rate (Address 1Ch) .................................................................... 67 6.24 ALC Release Rate (Address 1Dh) ................................................................................. 68 6.25 ALC Threshold (Address 1Eh) ....................................................................................... 69 6.26 Noise Gate Configuration & Misc. (Address 1Fh) .......................................................... 70 6.27 Status (Address 20h) (Read Only) ................................................................................ 71 6.28 Charge Pump Frequency (Address 21h) ....................................................................... 71 ANALOG PERFORMANCE PLOTS ...................................................................................... 72 7.1 Headphone THD+N versus Output Power Plots ............................................................. 72 7.2 ADC_FILT+ Capacitor Effects on THD+N ....................................................................... 74 EXAMPLE SYSTEM CLOCK FREQUENCIES ...................................................................... 75 8.1 Auto Detect Enabled ........................................................................................................ 75 8.2 Auto Detect Disabled ....................................................................................................... 76 PCB LAYOUT CONSIDERATIONS ....................................................................................... 77 9.1 Power Supply, Grounding ................................................................................................ 77 9.2 QFN Thermal Pad ........................................................................................................... 77 DS679A2
5. 6.
7.
8.
9.
4
CS42L51
10. ADC & DAC DIGITAL FILTERS .......................................................................................... 78 11. PARAMETER DEFINITIONS ................................................................................................ 79 12. PACKAGE DIMENSIONS ................................................................................................... 80 THERMAL CHARACTERISTICS............................................................................................ 80 13. ORDERING INFORMATION ............................................................................................... 81 14. REFERENCES ...................................................................................................................... 81 15. REVISION HISTORY ........................................................................................................... 82
DS679A2
5
CS42L51
LIST OF FIGURES
Figure 1. Typical Connection Diagram (Software Mode) .......................................................................... Figure 2. Typical Connection Diagram (Hardware Mode)......................................................................... Figure 3. Headphone Output Test Load.................................................................................................... Figure 4. Serial Audio Interface Slave Mode Timing................................................................................. Figure 5. TDM Serial Audio Interface Timing ............................................................................................ Figure 6. Serial Audio Interface Master Mode Timing............................................................................... Figure 7. Control Port Timing - IC ............................................................................................................ Figure 8. Control Port Timing - SPI Format............................................................................................... Figure 9. Analog Input Architecture........................................................................................................... Figure 10. MIC Input Mix w/Common Mode Rejection.............................................................................. Figure 11. Differential Input....................................................................................................................... Figure 12. ALC .......................................................................................................................................... Figure 13. Noise Gate Attenuation............................................................................................................ Figure 14. Output Architecture .................................................................................................................. Figure 15. De-Emphasis Curve................................................................................................................. Figure 16. Beep Configuration Options..................................................................................................... Figure 17. Peak Detect & Limiter .............................................................................................................. Figure 18. Master Mode Timing ................................................................................................................ Figure 19. Tri-State Serial Port ................................................................................................................. Figure 20. IS Format ................................................................................................................................ Figure 21. Left-Justified Format ................................................................................................................ Figure 22. Right-Justified Format (DAC only) ........................................................................................... Figure 23. Initialization Flow Chart............................................................................................................ Figure 24. Control Port Timing in SPI Mode ............................................................................................. Figure 25. Control Port Timing, IC Write.................................................................................................. Figure 26. Control Port Timing, IC Read.................................................................................................. Figure 27. AIN & PGA Selection ............................................................................................................... Figure 28. THD+N vs. Ouput Power per Channel at 1.8 V (16 load) .................................................... Figure 29. THD+N vs. Ouput Power per Channel at 2.5 V (16 load) .................................................... Figure 30. THD+N vs. Ouput Power per Channel at 1.8 V (32 load) .................................................... Figure 31. THD+N vs. Ouput Power per Channel at 2.5 V (32 load) .................................................... Figure 32. ADC THD+N vs. Frequency w/Capacitor Effects..................................................................... Figure 33. ADC Passband Ripple ............................................................................................................. Figure 34. ADC Stopband Rejection ......................................................................................................... Figure 35. DAC Passband Ripple ............................................................................................................. Figure 36. DAC Stopband ......................................................................................................................... Figure 35. DAC Transition Band ............................................................................................................... Figure 36. DAC Transition Band (Detail)................................................................................................... Figure 35. ADC Transition Band ............................................................................................................... Figure 36. ADC Transition Band (Detail)................................................................................................... 10 11 19 21 21 21 22 23 28 30 30 31 32 33 33 34 35 38 38 39 39 39 41 42 43 43 53 72 72 73 73 74 78 78 78 78 78 78 78 78
6
DS679A2
CS42L51 1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE
SDOUT (M/S)
DGND
MCLK
SCLK
SDIN
VD
32
31
30
29
28
27
VL
26
LRCK SDA/CDIN (MCLKDIV2) SCL/CCLK (IS/LJ) AD0/CS (DEM) VA_HP FLYP GNDHP FLYN
RESET
25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22
AIN1B AIN1A AFILTB AFILTA AIN2B/BIAS AIN2A MICIN2/BIAS/AIN3B MICIN1/AIN3A
CS42L51
21 20 19 18 17
VQ
Pin Name
LRCK SDA/CDIN (MCLKDIV2) SCL/CCLK (IS/LJ) AD0/CS (DEM) VA_HP FLYP GNDHP FLYN VSS_HP AOUTB AOUTA VA AGND
#
1 2
Pin Description
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Serial Control Data (Input/Output) - SDA is a data I/O in IC mode. CDIN is the input data line for the control port interface in SPI mode. MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry. Serial Control Port Clock (Input) - Serial clock for the serial control port. Interface Format Selection (Input) - Hardware Mode: Selects between IS & Left-Justified interface formats for the ADC & DAC.
3
4
Address Bit 0 (IC) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in IC mode; CS is the chip select signal for SPI format. De-Emphasis (Input) - Hardware Mode: Enables/disables the de-emphasis filter. Analog Power For Headphone (Input) - Positive power for the internal analog headphone section. Charge Pump Cap Positive Node (Input) - Positive node for the external charge pump capacitor. Analog Ground (Input) - Ground reference for the internal headphone/charge pump section. Charge Pump Cap Negative Node (Input) - Negative node for the external charge pump capacitor. Negative Voltage From Charge Pump (Output) - Negative voltage rail for the internal analog headphone section. Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table. Analog Power (Input) - Positive power for the internal analog section. Analog Ground (Input) - Ground reference for the internal analog section.
5 6 7 8 9 10 11 12 13
DS679A2
DAC_FILT+
ADC_FILT+
AOUTA
VSS_HP
AOUTB
AGND
VA
7
CS42L51
DAC_FILT+ ADC_FILT+ VQ MICIN1/ AIN3A MICIN2/ BIAS/AIN3B AIN2A AIN2B/BIAS 14 16 15 17 18 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. Microphone Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Microphone Input 2 (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specification table. This pin can also be configured as an output to provide a low noise bias supply for an external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table. Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Analog Input (Input/Output) - The full-scale level is specified in the ADC Analog Characteristics specification table. This pin can also be configured as an output to provide a low noise bias supply for an external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table. Filter Connection (Output) - Filter connection for the ADC inputs. Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Reset (Input) - The device enters a low power mode when this pin is driven low. Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and host control port. Refer to the Recommended Operating Conditions for appropriate voltages. Digital Power (Input) - Positive power for the internal digital section. Digital Ground (Input) - Ground reference for the internal digital section. Serial Audio Data Output (Output) - Output for two's complement serial audio data. Serial Port Master/Slave (Input/Output) - Hardware Mode Startup Option: Selects between master and slave mode for the serial port. 30 31 32 Master Clock (Input) -Clock source for the delta-sigma modulators. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Serial Audio Data Input (Input) - Input for two's complement serial audio data. Thermal relief pad for optimized heat dissipation. See "QFN Thermal Pad" on page 77.
19 20
AFILTA AFILTB AIN1A AIN1B RESET VL VD DGND SDOUT (M/S) MCLK SCLK SDIN Thermal Pad
21 22 23 24 25 26 27 28 29
8
DS679A2
CS42L51
1.1 Digital I/O Pin Characteristics
The logic level for each input should adhere to the corresponding power rail and should not exceed the maximum ratings. Power Rail
VL
Pin Name SW/(HW)
RESET SCL/CCLK (IS/LJ) SDA/CDIN (MCLKDIV2) AD0/CS (DEM) MCLK LRCK SCLK SDOUT (M/S) SDIN
I/O
Input Input Input/Output Input Input Input/Output Input/Output Input/Output Input
Driver 1.8 V - 3.3 V, CMOS/Open Drain 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V, CMOS Table 1. I/O Power Rails
Receiver 1.8 V - 3.3 V 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V, with Hysteresis 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V 1.8 V - 3.3 V
DS679A2
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CS42L51 2. TYPICAL CONNECTION DIAGRAMS
+1.8 V or +2.5 V
1 F 0.1 F 0.1 F 0.1 F
See Note 4
+1.8 V or +2.5 V
1 F
Note 4: Series resistance in the path of the power supplies must be avoided. Any voltage drop on VA_HP will directly impact the negative charge pump supply (VSS_HP) and result in clipping on the audio output .
VD
VA
VA_HP AOUTB
1.5 F
See Note 5
**
1 F
**
FLYP FLYN VSS_HP AOUTA
0.022 F 51.1
Headphone Out Left & Right
1.5 F
**
1 F
**
GND_HP
* *Use low ESR ceramic capacitors.
Note 2 : For best response to Fs/2 :
470 C Rext Line Level Out Left & Right See Note 2 Rext
CS42L51
470
C
Rext + 470 C= 4Fs (Rext x 470 )
This circuitry is intended for applications where the CS42L51 connects directly to an unbalanced output of the device. For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations. Note 5 : Larger capacitors, such as 1.5 F, improves the charge pump performance (and subsequent THD+N) at the full scale output power achieved with gain (G) settings greater than default.
Speaker Driver
AIN1A
1800 pF 1800 pF
* *
1 F
100
Left Analog Input 1
100 k
MCLK SCLK LRCK Digital Audio Processor SDIN SDOUT RESET SCL/CCLK SDA/CDIN AD0/CS
AIN1B
1 F
100
100 k
Right Analog Input 1 Left Analog Input 2
100 k
AIN2A
1800 pF 1800 pF
* 1 F *
1 F
100
AIN2B BIAS1 MICIN1 AIN3A BIAS2 AIN3B/MICIN2
100
100 k
Right Analog Input 2
Microphone Input
1 F 100 k
Microphone Bias
0.1 F
RL
See Note 3
2k
2k
Note 3: The value of R L is dictated by the microphone cartridge.
+1.8 V, +2.5 V or +3.3 V
See Note 1 0.1 F
VL
ADC_FILT+ DAC_FILT+
1 F 10 F
Note 1: Resistors are required for IC control port operation
AGND
* *
1000 pF 1000 pF 1 F
AFILTA AFILTB VQ DGND
* Capacitors must be C0G or equivalent
Figure 1. Typical Connection Diagram (Software Mode)
10
DS679A2
CS42L51
+1.8V or +2.5V
1 F 0.1 F 0.1 F 0.1 F 1 F
Note 4: Series resistance in the path of the power supplies (typically used for added filtering) must be avoided. Any voltage drop on VA_HP will directly impact the negative charge pump supply (VSS_HP) and result in clipping on the audio output . See Note 4
+1.8V or +2.5V
VD
VA
VA_HP AOUTB
1 F
**
FLYP FLYN AOUTA
0.022 F 51.1
Headphone Out Left & Right
1 F
**
VSS_HP GND_HP
470 C
Rext Line Level Out Left & Right See Note 2
* *Use low ESR ceramic capacitors.
CS42L51
470
C
Rext
MCLK SCLK LRCK
VL
Speaker Driver
SDIN SDOUT/ M/S
AIN1A
1800 pF * 1 F 100 1800 pF * 100 1 F
Left Analog Input 1
100 k 100 k
Digital Audio Processor
AIN1B RESET IS/LJ MCLKDIV2 DEM AGND
* * 1000 pF
Right Analog Input 1
ADC_FILT+ DAC_FILT+
1 F 10 F
+1.8V, 2.5 V or +3.3V
0.1 F
VL DGND
AFILTA AFILTB VQ
1000 pF
1 F
* Capacitors must be C0G or equivalent
Note 2 : This circuitry is intended for applications where the CS 42L51 connects directly to an unbalanced output of the device . For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations . For best response to Fs/2 :
C=
Rext + 470 4Fs(Rext x 470 )
Figure 2. Typical Connection Diagram (Hardware Mode)
DS679A2
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CS42L51 3. CHARACTERISTIC AND SPECIFICATION TABLES
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25 C.)
SPECIFIED OPERATING CONDITIONS
(AGND=DGND=0 V, all voltages with respect to ground.)
Parameters
DC Power Supply (Note 1) Analog Core Headphone Amplifier Digital Core Serial/Control Port Interface
Symbol
VA VA_HP VD VL
Min
1.71 2.37 1.71 2.37 1.71 2.37 1.71 2.37 3.14 -10 -40
Nom
1.8 2.5 1.8 2.5 1.8 2.5 1.8 2.5 3.3 -
Max
1.89 2.63 1.89 2.63 1.89 2.63 1.89 2.63 3.47 +70 +85
Units
V V V V V V V V V C C
Ambient Temperature Commercial - CNZ Automotive - DNZ TA
ABSOLUTE MAXIMUM RATINGS
(AGND = DGND = 0 V; all voltages with respect to ground.)
Parameters
DC Power Supply
Symbol
Min
-0.3 -0.3 -0.3 -
Max
3.0 3.0 4.0 10
Units
V V V mA
Input Current Analog Input Voltage Digital Input Voltage (Note 3)) Ambient Operating Temperature (power applied) Storage Temperature
Analog VA, VA_HP Digital VD Serial/Control Port Interface VL (Note 2) Iin (Note 3) VIN VIND Commercial - CNZ Automotive - DNZ TA Tstg
AGND-0.7
-0.3 -20 -50 -65
VA+0.7
VL+ 0.4 +85 +95 +150
V
V C C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes:
1. The device will operate properly over the full range of the analog, headphone amplifier, digital core and serial/control port interface supplies. 2. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 3. The maximum over/under voltage is limited by the input current.
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DS679A2
CS42L51 ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ)
(Test Conditions (unless otherwise specified): All supplies = VA = 2.5 V and 1.8 V; Input sine wave (relative to digital full-scale): 1 kHz through passive input filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz)
Parameter (Note 4)
Min
A-weighted unweighted -1 dBFS -20 dBFS -60 dBFS 93 90 -
VA = 2.5V Typ
99 96 -86 -76 -36
Max
-80 -
Min
90 87 -
VA = 1.8V Typ Max
96 93 -84 -73 -33 -78 -
Unit
dB dB dB dB dB
Analog In to ADC (PGA bypassed)
Dynamic Range Total Harmonic Distortion + Noise
Analog In to PGA to ADC Dynamic Range
PGA Setting: 0 dB PGA Setting: +12 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB PGA Setting: +12 dB A-weighted unweighted A-weighted unweighted -1 dBFS -60 dBFS -1 dBFS 92 89 85 82 98 95 91 88 -88 -35 -85 -82 -79 89 86 82 79 95 92 88 85 -86 -32 -83 -80 -77 dB dB dB dB dB dB dB
Analog In to MIC Pre-Amp(+16 dB) to PGA to ADC Dynamic Range
PGA Setting: 0 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB A-weighted unweighted -1 dBFS 86 83 -76 83 80 -74 dB dB dB
Analog In to MIC Pre-Amp(+32 dB) to PGA to ADC Dynamic Range
PGA Setting: 0 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB A-weighted unweighted -1 dBFS 78 74 -74 75 71 -71 dB dB dB
Other Characteristics
DC Accuracy Interchannel Gain Mismatch Gain Drift Input Interchannel Isolation DAC Isolation (Note 5) Full-scale Input Voltage (x*VA) (Note 7) Input Impedance (Note 6) 0.1 100 0.1 100 dB ppm/ C dB dB Vpp k k k
0.70*VA ADC 18 PGA 40 MIC 50
90 70 0.72*VA -
0.75*VA -
0.70*VA 18 40 50
90 70 0.72*VA -
0.75*VA -
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CS42L51 ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ)
(Test Conditions (unless otherwise specified): All supplies = VA = 2.5 V and 1.8 V; Input sine wave (relative to fullscale): 1 kHz through passive input filter; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz)
Parameter (Note 4)
Min
A-weighted unweighted -1 dB -20 dB -60 dB 91 78 -
VA = 2.5V Typ
99 96 -86 -76 -36
Max
-78 -
Min
88 85 -
VA = 1.8V Typ
96 93 -84 -73 -33
Max
-76 -
Unit
dB dB dB dB dB
Analog In to ADC
Dynamic Range Total Harmonic Distortion + Noise
Analog In to PGA to ADC Dynamic Range
PGA Setting: 0 dB PGA Setting: +12 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB PGA Setting: +12 dB A-weighted unweighted A-weighted unweighted -1 dB -60 dB -1 dB 90 87 83 80 98 95 91 88 -88 -35 -85 -80 -77 87 84 80 77 95 92 88 85 -86 -32 -83 -78 -75 dB dB dB dB dB dB dB
Analog In to MIC Pre-Amp(+16 dB) to PGA to ADC Dynamic Range
PGA Setting: 0 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB A-weighted unweighted -1 dB 86 83 -76 83 80 -74 dB dB dB
Analog In to MIC Pre-Amp(+32 dB) to PGA to ADC Dynamic Range
PGA Setting: 0 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB A-weighted unweighted -1 dB 78 74 -74 75 71 -71 dB dB dB
Other Characteristics
DC Accuracy Interchannel Gain Mismatch Gain Drift Input Interchannel Isolation DAC Isolation (Note 5) Full-scale Input Voltage (Note 7) Input Impedance (Note 6) 0.1 100 0.1 100 dB ppm/ C dB dB Vpp k k k
0.70*VA ADC 18 PGA 40 MIC 50
90 70 0.72*VA -
0.75*VA -
0.70*VA 18 40 50
90 70 0.72*VA -
0.75*VA -
Notes:
4. Referred to the typical full-scale voltage. 5. Measured with DAC delivering full-scale output power into 16 .
14
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CS42L51
Notes:
6. Measured between AINxx and AGND. 7. Full-scale input voltage characteristics for the PGA and Microphone inputs are scaled based on the gain setting for each.
ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Note 8)
Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay to -0.1 dB corner
Min
0 -0.09 0.6677 48.4 -
Typ
2.7/Fs 3.7 24.2 10 105/Fs
Max
0.4948 0 0.17 0
Unit
Fs dB Fs dB s Hz Hz Deg dB s
High-Pass Filter Characteristics
Frequency Response Phase Deviation Passband Ripple Filter Settling Time -3.0 dB -0.13 dB @ 20 Hz -
Notes:
8. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 33 to 36 on page 78) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
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15
CS42L51 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ)
(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 k, CL = 10 pF for the line output (see Figure 3), and test load RL = 16 , CL = 10 pF (see Figure 3) for the headphone output. HP_GAIN[2:0] = 011.)
Parameter (Note 9)
Min
RL = 10 k Dynamic Range
18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit A-weighted unweighted A-weighted unweighted 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB 92 89 -
VA = 2.5V Typ
Max Min
VA = 1.8V Typ
Max
Unit
98 95 96 93 -86 -75 -35 -86 -73 -33
-80 -
89 86 -
95 92 93 90 -88 -72 -32 -88 -70 -30
-82 -
dB dB dB dB dB dB dB dB dB dB
16-Bit
RL = 16
Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit A-weighted unweighted A-weighted unweighted 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB 92 89 98 95 96 93 -75 -75 -35 -75 -73 -33 -69 89 86 95 92 93 90 -75 -72 -32 -75 -70 -30 -69 dB dB dB dB dB dB dB dB dB dB
16-Bit
Other Characteristics for RL = 16 or 10 k
Output Parameters Modulation Index (MI) (Note 10) Analog Gain Multiplier (G) Full-scale Output Voltage (2*G*MI*VA) (Note 10) Full-scale Output Power (Note 10) Interchannel Isolation (1 kHz) Interchannel Gain Mismatch Gain Drift AC-Load Resistance (RL) Load Capacitance (CL) (Note 11) (Note 11) 16 10 k 0.6787 0.6787 0.6047 0.6047 Refer to Table "Line Output Voltage Characteristics" on Vpp page 18 Refer to Table "Headphone Output Power Characteristics" on page 19 80 80 dB 95 93 dB 0.1 0.25 0.1 0.25 dB 100 100 ppm/ C 16 16 150 150 pF
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CS42L51 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ)
(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz and 96 kHz; test load RL = 10 k, CL = 10 pF for the line output (see Figure 3), and test load RL = 16 , CL = 10 pF (see Figure 3) for the headphone output. HP_GAIN[2:0] = 011.)
Parameter (Note 9)
Min
RL = 10 k Dynamic Range
18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit A-weighted unweighted A-weighted unweighted 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB 90 87 -
VA = 2.5V Typ
Max
Min
VA = 1.8V Typ
Max
Unit
98 95 96 93 -86 -75 -35 -86 -73 -33
-78 -
87 84 -
95 92 93 90 -88 -72 -32 -88 -70 -30
-80 -
dB dB dB dB dB dB dB dB dB dB
16-Bit
RL = 16 Dynamic Range
18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit A-weighted unweighted A-weighted unweighted 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB 90 87 98 95 96 93 -75 -75 -35 -75 -73 -33 -67 87 84 95 92 93 90 -75 -72 -32 -75 -70 -30 -67 dB dB dB dB dB dB dB dB dB dB
16-Bit
Other Characteristics for RL = 16 or 10 k
Output Parameters Modulation Index (MI) (Note 10) Analog Gain Multiplier (G) Full-scale Output Voltage (2*G*MI*VA) (Note 10) Full-scale Output Power (Note 10) Interchannel Isolation (1 kHz) Interchannel Gain Mismatch Gain Drift AC-Load Resistance (RL) Load Capacitance (CL) (Note 11) (Note 11) 16 10 k 0.6787 0.6787 0.6047 0.6047 Refer to Table "Line Output Voltage Characteristics" on Vpp page 18 Refer to Table "Headphone Output Power Characteristics" on page 19 80 80 dB 95 93 dB 0.1 0.25 0.1 0.25 dB 100 100 ppm/ C 16 16 150 150 pF
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CS42L51 LINE OUTPUT VOLTAGE CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 k, CL = 10 pF (see Figure 3).
Parameter
Min
AOUTx Voltage Into RL = 10 k
HP_GAIN[2:0] 000 001 010 011 (default) 100 101 110 111 Analog Gain (G) 0.3959 0.4571 0.5111 0.6047 0.7099 0.8399 1.0000 1.1430 VA_HP 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.95 -
VA = 2.5V Typ
Max
Min
VA = 1.8V Typ
Max
Unit
1.34 1.34 1.55 1.55 1.73 1.73 2.05 2.05 2.41 2.41 2.85 2.85 3.39 3.39 (See (Note 12) 3.88
2.15 -
1.41 -
0.97 0.97 1.12 1.12 1.25 1.25 1.48 1.48 1.73 1.73 2.05 2.05 2.44 2.44 2.79 2.79
1.55 -
Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp
18
DS679A2
CS42L51 HEADPHONE OUTPUT POWER CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 16 , CL = 10 pF (see Figure 3).
Parameter
Min
AOUTx Power Into RL = 16
HP_GAIN[2:0] 000 001 010 011 (default) 100 101 Analog Gain (G) 0.3959 0.4571 0.5111 0.6047 0.7099 0.8399 VA_HP 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V -
VA = 2.5V Typ
Max
Min
VA = 1.8V Typ
Max
Unit
110 111
1.0000 1.1430
7 7 10 10 12 12 17 17 23 23 (Note 10)) See Figure 28 on page 72 32 (Note 10, 12) See Figures 28 and 29 on page 72
14 14 19 19 23 23 (Note 12) 32 (Note 12) 44
-
mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms
Notes:
9. One-half LSB of triangular PDF dither is added to data. 10. Full-scale output voltage and power is determined by the gain setting, G, in register "Headphone Analog Gain (HP_GAIN[2:0])" on page 54. High gain settings at certain VA and VA_HP supply levels may cause clipping when the audio signal approaches full-scale, maximum power output, as shown in Figures 28 - 31 on page 73. 11. See Figure 3. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recommended 150 pF can cause the internal op-amp to become unstable. 12. VA_HP settings lower than VA reduces the headroom of the headphone amplifier. As a result, the DAC may not achieve the full THD+N performance at full-scale output voltage and power.
AOUTx
51 0.022 F
C
L
R
L
AGND
Figure 3. Headphone Output Test Load
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19
CS42L51 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameter (Note 13))
Frequency Response 10 Hz to 20 kHz Passband StopBand StopBand Attenuation (Note 14) Group Delay De-emphasis Error Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz to -0.05 dB corner to -3 dB corner
Min
-0.01 0 0 0.5465 50 -
Typ
9/Fs -
Max
+0.08 0.4780 0.4996 +1.5/+0 +0.05/-0.25 -0.2/-0.4
Unit
dB Fs Fs Fs dB s dB dB dB
Notes:
13. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 35 and 36 on page 78) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 14. Measurement Bandwidth is from Stopband to 3 Fs.
SWITCHING SPECIFICATIONS - SERIAL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT CLOAD = 15 pF.)
Parameters
RESET pin Low Pulse Width
MCLK Frequency MCLK Duty Cycle (Note 16) (Note 15)
Symbol
Min
1 1.024 45
Max
38.4 55
Units
ms MHz %
Slave Mode
Input Sample Rate (LRCK) Quarter-Speed Mode Half-Speed Mode Single-Speed Mode Double-Speed Mode Fs Fs Fs Fs 1/tP ts(LK-SK) td(MSB) ts(SDO-SK) th(SK-SDO) ts(SD-SK) th 4 8 4 50 45 45 40 30 30 20 20 12.5 25 50 100 55 64*Fs 55 40 kHz kHz kHz kHz % Hz % ns ns ns ns ns ns
LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle LRCK Setup Time Before SCLK Rising Edge LRCK Edge to SDOUT MSB Output Delay SDOUT Setup Time Before SCLK Rising Edge SDOUT Hold Time After SCLK Rising Edge SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge
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CS42L51
//
LRCK
ts(LK-SK) // // // td(MSB) th(SK-SDO) // MSB // th // MSB // ts(SDO-SK) MSB-1 tP
SCLK
SDOUT
ts(SD-SK)
SDIN
MSB-1
Figure 4. Serial Audio Interface Slave Mode Timing
Parameters
Master Mode (Note 17)
Output Sample Rate (LRCK) All Speed Modes
Symbol
Fs
Min
-
Max
MCLK ---------------128
55 64*Fs 55
Units
Hz
LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle SCLK Rising Edge to SDOUT Output Delay LRCK Edge to SDOUT MSB Output Delay SDOUT Setup Time Before SCLK Rising Edge SDOUT Hold Time After SCLK Rising Edge SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge td td(MSB) ts(SDO-SK) th(SK-SDO) ts(SD-SK) th 1/tP
45 45 30 30 20 20
% Hz % s ns ns ns ns ns
1 ---------------MCLK
40 -
Notes:
15. After powering up the CS42L51, RESET should be held low after the power supplies and clocks are settled. 16. See "Example System Clock Frequencies" on page 75 for typical MCLK frequencies. 17. See "Master" on page 38.
//
LRCK
// tP // // td(MSB) th(SK-SDO) // MSB // th // MSB // ts(SDO-SK) MSB-1
SCLK
SDOUT
ts(SD-SK)
SDIN
MSB-1
Figure 6. Serial Audio Interface Master Mode Timing
DS679A2
21
CS42L51 SWITCHING SPECIFICATIONS - IC CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL = 30 pF)
Parameter
SCL Clock Frequency
Symbol
fscl tirs tbuf thdst tlow thigh tsust (Note 18) thdd tsud trc tfc tsusp tack
Min
500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300
Max
100 1 300 1000
Unit
kHz ns s s s s s s ns s ns s ns
RESET Rising Edge to Start
Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling
Notes:
18. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST t irs Stop SDA t buf
SCL Repeated Start
Start
Stop
t hdst
t high
t
hdst
tf
t susp
t
low
t
hdd
t sud
t sust
tr
Figure 7. Control Port Timing - IC
22
DS679A2
CS42L51 SWITCHING CHARACTERISTICS - SPI CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL)
Parameter
CCLK Clock Frequency
Symbol
fsck tsrs tcss tcsh tscl tsch tdsu (Note 19) (Note 20) (Note 20) tdh tr2 tf2
Min
0 20 20 1.0 66 66 40 15 -
Max
6.0 100 100
Units
MHz ns ns s ns ns ns ns ns ns
RESET Rising Edge to CS Falling
CS Falling to CCLK Edge CS High Time Between Transmissions CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN
Notes:
19. Data must be held for sufficient time to bridge the transition time of CCLK. 20. For fsck <1 MHz.
RST
tsrs
CS
tcsh tcss tsch tscl tr2
CCLK
tf2 tdsu tdh
CDIN
Figure 8. Control Port Timing - SPI Format
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23
CS42L51 DC ELECTRICAL CHARACTERISTICS
(AGND = 0 V; all voltages with respect to ground.)
Parameters
VQ Characteristics
Nominal Voltage Output Impedance DC Current Source/Sink (Note 21) DAC_FILT+ Nominal Voltage ADC_FILT+ Nominal Voltage
Min
MICBIAS_LVL[1:0] = 00 MICBIAS_LVL[1:0] = 01 MICBIAS_LVL[1:0] = 10 MICBIAS_LVL[1:0] = 11 1 kHz 1 kHz -
Typ
0.5*VA 23 VA VA -0.8*(VA_HP)
Max
10 10 1 -
Units
V k A V V V A V V V V mA dB dB
VSS_HP Characteristics
Nominal Voltage DC Current Source
MIC BIAS Characteristics
Nominal Voltage 0.8*VA 0.7*VA 0.6*VA 0.5*VA 50 60
DC Current Source Power Supply Rejection Ratio (PSRR) Power Supply Rejection Ratio (PSRR) (Note 22)
Notes:
21. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage through electrolytic de-coupling capacitors. 22. Valid with the recommended capacitor values on DAC_FILT+, ADC_FILT+ and VQ. Increasing the capacitance will also increase the PSRR.
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
Parameters (Note 23)
Input Leakage Current Input Capacitance 1.8 V - 3.3 V Logic High-Level Output Voltage (IOH = -100 A) Low-Level Output Voltage (IOL = 100 A) High-Level Input Voltage Low-Level Input Voltage VOH VOL VIH VIL VL - 0.2 0.65*VL 0.2 0.35*VL V V V V
Symbol
Iin
Min
-
Max
10 10
Units
A pF
23. See "Digital I/O Pin Characteristics" on page 9 for serial and control port power rails.
24
DS679A2
CS42L51 POWER CONSUMPTION
See (Note 24).
Power Ctl. Registers 02h 03h
PDN_DACB PDN_DACA PDN_PGAB PDN_PGAA PDN_ADCB PDN_ADCA PDN PDN_MICB PDN_MICA PDN_MICBIAS
Typical Current (mA)
Operation 1 2 3 Off (Note 25) Standby (Note 26) Mono Record ADC PGA to ADC MIC to PGA to ADC (with Bias) MIC to PGA to ADC (no Bias) 4 Stereo Record ADC PGA to ADC MIC to PGA to ADC (no Bias) 5 6 7 8 9 Mono Playback Stereo Playback Mono Record & Playback PGA in (no MIC) to Mono Out Phone Monitor MIC (w/bias) in to Mono Out Stereo Record & Playback PGA in (no MIC) to Stereo Out
V
x x x x x x x x x x 1.8 2.5 x x x x x x 1 x x x 1.8 2.5 1 1 1 1 1 0 0 1 1 1 1.8 2.5 1 1 1 0 1 0 0 1 1 1 1.8 2.5 1 1 1 0 1 0 0 1 0 0 1.8 2.5 1 1 1 0 1 0 0 1 0 1 1.8 2.5 1 1 1 1 0 0 0 1 1 1 1.8 2.5 1 1 0 0 0 0 0 1 1 1 1.8 2.5 1 1 0 0 0 0 0 0 0 1 1.8 2.5 1 0 1 1 1 1 0 1 1 1 1.8 2.5 0 0 1 1 1 1 0 1 1 1 1.8 2.5 1 0 1 0 1 0 0 1 1 1 1.8 2.5 1 0 1 0 1 0 0 1 0 0 1.8 2.5 0 0 0 0 0 0 0 1 1 1 1.8 2.5
VA_HP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1.66 2.03 2.77 3.21 1.66 2.03 1.66 2.03 2.77 3.21
VA 0 0 0.01 0.01 1.85 2.07 2.35 2.58 3.67 3.95 3.27 3.52 2.69 2.93 3.65 3.91 5.48 5.76 1.40 1.71 2.05 2.50 3.63 4.16 4.95 5.52 5.59 6.28
VD 0 0 0.02 0.03 2.03 3.05 2.03 3.08 2.05 3.09 2.03 3.08 2.12 3.18 2.12 3.17 2.11 3.17 2.35 3.48 2.35 3.49 2.73 4.08 2.75 4.08 2.82 4.19
Total Power VL (Note 27) (mWrms)
0 0 0 0 0.03 0.05 0.03 0.05 0.03 0.05 0.03 0.05 0.03 0.04 0.03 0.04 0.03 0.04 0.01 0.02 0.01 0.02 0.03 0.05 0.03 0.05 0.03 0.04 0 0 0.05 0.10 7.05 12.94 7.95 14.29 10.36 17.71 9.61 16.62 8.72 15.40 10.45 17.84 13.73 22.45 9.74 18.08 12.93 23.02 14.49 25.79 16.90 29.20 20.18 34.30
Notes:
24. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate = 48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode and master/slave operation. 25. RESET pin 25 held LO, all clocks and data lines are held LO. 26. RESET pin 25 held HI, all clocks and data lines are held HI. 27. VL current will slightly increase in master mode.
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25
CS42L51 4. APPLICATIONS
4.1 4.1.1 Overview Architecture
The CS42L51 is a highly integrated, low power, 24-bit audio CODEC comprised of stereo analog-to-digital converters (ADC), and stereo digital-to-analog converters (DAC) designed using multi-bit delta-sigma techniques. The DAC operates at an oversampling ratio of 128Fs and the ADC operates at 64Fs, where Fs is equal to the system sample rate. The different clock rates maximize power savings while maintaining high performance. The CODEC operates in one of four sample rate speed modes: Quarter, Half, Single and Double. It accepts and is capable of generating serial port clocks (SCLK, LRCK) derived from an input Master Clock (MCLK).
4.1.2
Line & MIC Inputs
The analog input portion of the CODEC allows selection from and configuration of multiple combinations of stereo and microphone (MIC) sources. Six line inputs with configuration for two MIC inputs (or one MIC input with common mode rejection), two MIC bias outputs and independent channel control (including a high-pass filter disable function) are available. A Programmable Gain Amplifier (PGA), MIC boost, and Automatic Level Control (ALC), with noise gate settings, provide analog gain and adjustment. Digital volume controls, including gain, boost, attenuation and inversion are also available.
4.1.3
Line & Headphone Outputs
The analog output portion of the CODEC includes a headphone amplifier capable of driving headphone and line-level loads. An on-chip charge pump creates a negative headphone supply allowing a full-scale output swing centered around ground. This eliminates the need for large DC-Blocking capacitors and allows the amplifier to deliver more power to headphone loads at lower supply voltages. Eight gain settings for the headphone amplifier are available.
4.1.4
Signal Processing Engine
A signal processing engine is available to process serial input data (PCM) and ADC data before output to the DAC. The ADC and PCM data have independent volume controls and mixing functions such as mono mixes and left/right channel swaps. A Tone Control provides bass and treble at four selectable corner frequencies. An automatic level control provides limiting capabilities at programmable attack and release rates, maximum thresholds and soft ramping. A 15/50 s de-emphasis filter is also available at a 44.1 kHz sample rate.
4.1.5
Beep Generator
A beep may be generated internally at select frequencies across approximately two octave major scales and configured to occur continuously, periodically or at single time intervals controlled by the user. Volume may be controlled independently.
4.1.6
Device Control (Hardware or Software Mode)
In software mode, all functions and features may be controlled via a two-wire IC or three-wire SPI control port interface. In hardware mode, a limited feature set may be controlled via stand-alone control pins.
4.1.7
Power Management
Two software mode control registers provide independent power down control of the ADC, DAC, PGA, MIC pre-amp and MIC bias, allowing operation in select applications with minimal power consumption.
26
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CS42L51
4.2 Hardware Mode
A limited feature-set is available when the CODEC powers up in hardware mode (see "Recommended Power-Up Sequence" on page 40) and may be controlled via stand-alone control pins. Table 2 shows a list of functions/features, the default configuration and the associated stand-alone control available.
Feature/Function
Power Control
Auto Detect Speed Mode MCLK Divide
Hardware Mode Feature/Function Summary Default Configuration Stand-Alone Control CODEC Powered Up PGAx Powered Up ADCx Powered Up DACx Powered Up MIC Bias Powered Down MICx Pre-amplifier Powered Down Enabled Serial Port Slave Auto-Detect Speed Mode Serial Port Master Single-Speed Mode "MCLKDIV2" pin 2 (Selectable)
(Selectable)
ADC DAC Digital Boost Soft Ramp Zero Cross Invert PGAx Attenuator ALC Noise Gate
Note
-
see Section 4.5 on page 37 see Section 4.5 on page 37 see Section 4.6 on page 39 -
Serial Port Master / Slave Selection Interface Control ADC Volume & Gain
"M/S" pin 29 "IS/LJ" pin 3 -
(Selectable) Disabled Disabled Disabled Disabled 0 dB 0 dB Disabled Disabled Enabled Continuous DC Subtraction AIN1A to PGAA AIN1B to PGAB G = 0.6047 0 dB Disabled Enabled Disabled Disabled (Selectable) Disabled Disabled Disabled Disabled Data Input (PCM) to DAC ADCA = L; ADCB = R PCMA = L; PCMB = R (64xFs)/7
ADCx High-Pass Filter ADCx High-Pass Filter Freeze Line/MIC Input Select DAC Volume & Gain HP Gain AOUTx Volume Invert Soft Ramp Zero Cross Ramp
-
-
DAC De-Emphasis Signal Processing Engine (SPE) MIX Beep Tone Control Peak Detect & Limiter ADC DAC
"DEM" pin 4 -
see Section 4.4.1 on page 33 -
Data Selection Channel Mix Charge Pump Frequency
-
-
Table 2. Hardware Mode Feature Summary
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27
CS42L51
4.3 Analog Inputs
AINxA and AINxB are the analog inputs, internally biased to VQ, that accepts line-level and MIC-level signals, allowing various gain and signal adjustments for each channel.
ADCA_MUTE ADCA_DBOOST ADCA_ATT[7:0] 0/-96dB 1dB steps PDN_ADCA PGAA_VOL[5:0] ADC_SNGVOL SOFTA ZCROSSA +12/-3dB 0.5dB steps
MUX
MUX
+20dB Digital Boost
ADCA_HPF FREEZE ADCA_HPF ENABLE ALCA_SRDIS ALCA_ZCDIS ALC_ENA
Attenuator
Multibit Oversampling ADC
INV_ADCA
PGA
PDN_PGAA
MUX
+16/ 32 dB
AIN1A AIN2A AIN3A/ MICIN1
MICA_BOOST PDN_MICA
SOFTA
AINA_MUX[1:0]
PCM Serial Interface
MICBIAS_LVL[1:0]
DIGMIX
MICMIX
ALC_ARATE[5:0] ALC_RRATE[5:0] MAX[2:0] MIN[2:0] ALC_ENB ALCB_SRDIS ALCB_ZCDIS
ALC
Noise Gate
NG_ALL NG_EN THRESH[3:0] NGDELAY[1:0]
MICBIAS
PDN_MICBIAS
ADCB_DBOOST SOFTB
PDN_ADCB
PGAB_VOL[5:0] ADC_SNGVOL SOFTB ZCROSSB +12/-3dB 0.5dB steps
MICBIAS_SEL
MUX
MUX
+20dB Digital Boost
ADCB_HPF FREEZE ADCB_HPF ENABLE
Attenuator
Multibit Oversampling ADC
INV_ADCB
PGA
PDN_PGAB
MUX
+16/ 32 dB
AIN1B AIN2B/MICBIAS AIN3B/ MICIN2/ MICBIAS
MICB_BOOST PDN_MICB
ADCB_MUTE ADCB_ATT[7:0] 0/-96dB 1dB steps
AINB_MUX[1:0]
TO SIGNAL PROCESSING ENGINE (SPE) FROM SIGNAL PROCESSING ENGINE (SPE)
Figure 9. Analog Input Architecture
4.3.1
Digital Code, Offset & DC Measurement
The ADC output data is in two's complement binary format. For inputs above positive full-scale or below negative full-scale, the ADC will output 7FFFFFH or 800000H, respectively and cause the ADC overflow bit to be set to a `1'. Given the two's complement format, low-level signals may cause the MSB of the serial data to periodically toggle between `1' and `0', possibly introducing noise into the system as the bit switches back and forth. To prevent this phenomena, a constant DC offset is added to the serial data bringing the low-level signal just above the point at which the MSB would normally toggle, thus reducing the noise introduced. The CODEC may be used to measure DC voltages by disabling the high-pass filter for the designated channel. DC levels are measured relative to VQ and will be decoded as positive two's complement binary numbers above VQ and negative two's complement binary numbers below VQ.
Software Controls: "Status (Address 20h) (Read Only)" on page 71, "ADC Control (Address 06h)" on page 52.
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4.3.2 High-Pass Filter and DC Offset Calibration
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the high-pass filter is "frozen" during normal operation, the current value of the DC offset for the corresponding channel is held. It is this DC offset that will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: 1. 1) Running the CODEC with the high-pass filter enabled and the DC offset not "frozen" until the filter settles. See the Digital Filter Characteristics for filter settling time. 2. Freezing the DC offset. The high-pass filters are controlled using the ADCx_HPFRZ and ADCx_HPFEN bits. If a particular ADC channel is used to measure DC voltages, the high-pass filter may be disabled using the ADCx_HPFEN bit.
Software Controls: "ADC Control (Address 06h)" on page 52.
4.3.3
Digital Routing
The digital output of the ADC may be internally routed to the signal processing engine for playback of analog input signals. Volume to the DAC may be controlled using the ADCMIX[6:0] bits. The serial input data may also be routed to the ADC serial interface using the DIGMIX bit. This is useful for recording a digital mix along with the analog input.
Software Controls: "ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh)" on page 58, "Interface Control (Address 04h)" on page 49.
4.3.4
Differential Inputs
The stereo pair inputs act as a single differential input when the MICMIX bit is enabled. This provides common mode rejection of noise in digitally intense PCB's where the microphone signal traverses long traces, or across long microphone cables as illustrated in Figure 10. Since the mixer provides a differential combination of the two signals, the potential input mix may exceed the maximum full-scale input and result in clipping. The level out of the mixer, therefore, is automatically attenuated 6 dB. Gain may be applied using either the analog PGA or MIC Pre-amp or the digital ADCMIX volume control to re-adjust a small signal to desired levels. The analog inputs may also be used as a differential input pair as illustrated in Figure 11. The two channels are differentially combined when the MICMIX bit is enabled.
4.3.4.1
External Passive Components
The microphone input is internally biased to VQ. Input signals must be AC coupled using external capacitors with values consistent with the desired high-pass filter design. The MICINx input resistance of 50 k may be combined with an external capacitor of 1 F to achieve the cutoff frequency defined by the equation,
f c 1 = ------------------------------------------ = 3.18Hz 2 ( 50k ) ( 1F )
An electrolytic capacitor must be placed such that the positive terminal is positioned relative to the side with the greater bias voltage. The MICBIAS voltage level is controlled by the MICBIAS_LVL[1:0] bits.
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The MICBIAS series resistor must be selected based on the requirements of the particular microphone used. The MICBIAS output pin is selected using the MICBIAS_SEL bit.
Software Controls: "Interface Control (Address 04h)" on page 49, "MIC Control (Address 05h)" on page 51.
MICBIAS
20
//
+
MICIN1
17
//
+
MICIN2
18
Figure 10. MIC Input Mix w/Common Mode Rejection
2.5 V
2.15 V 1.25 V 0.35 V
VA AINxA
2.15 V 1.25 V 0.35 V
AINxB
Full-Scale Differential Input Level (MICMIX=1) = (AINxA - AINxB) = 3.6 VPP = 1.27 VRMS
Figure 11. Differential Input
4.3.5
Analog Input Multiplexer
A stereo 4-to-1 analog input multiplexer selects between a line-level input source, or a mic-level input source, depending on the PDN_PGAx and AINx_MUX[1:0] bit settings. Signals may be routed to or bypassed around the PGA. To conserve power, the PGA's may be powered down allowing the user to select from multiple line-level sources and route the stereo signal directly to the ADC. When using the MIC preamp, however, the PGA must be powered up. Analog input channel B may also be used as an output for the MIC bias voltage. The MICBIAS_SEL bit routes the bias voltage to either of two pins. The multiplexer must then select from the remainder of the two input channels. The ADC, PGA and MIC pre-amplifier each has an associated input resistance. When selecting between these paths, the input resistance to the CODEC will change accordingly. Refer to the input resistance characteristics in the Characteristic and Specification Tables for the input resistance of each path.
Software Controls: "Power Control 1 (Address 02h)" on page 47, "MIC Control (Address 05h)" on page 51, "ADCx Input Select, Invert & Mute (Address 07h)" on page 53.
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4.3.6 MIC & PGA Gain
The MIC-level input passes through a +16 dB or +32 dB analog gain stage prior to the input multiplexer, allowing it to be used for microphone level signals without the need for any external gain. The PGA must be powered up when using the MIC pre-amp. The PGA stage provides an additional +12 dB to -3 dB of analog gain in 0.5 dB steps.
Software Controls: "Power Control 1 (Address 02h)" on page 47, "ADCx Input Select, Invert & Mute (Address 07h)" on page 53, "ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh)" on page 56, "MIC Control (Address 05h)" on page 51.
4.3.7
Automatic Level Control (ALC)
When enabled, the ALC monitors the analog input signal after the digital attenuator, detects when peak levels exceed the maximum threshold settings and lowers, first, the PGA gain settings and then increases the digital attenuation levels at a programmable attack rate and maintains the resulting level below the maximum threshold. When input signal levels fall below the minimum threshold, digital attenuation levels are decreased first and the PGA gain is then increased at a programmable release rate and maintains the resulting level below the minimum threshold. Attack and release rates are affected by the ADC soft ramp/zero cross settings and sample rate, Fs. ALC soft ramp and zero cross dependency may be independently enabled/disabled. Recommended settings: Best level control may be realized with the fastest attack and slowest release setting with soft ramp enabled in the control registers. NOTE: When the ALC is enabled the PGA and Attenuator is automatically controlled and should not be adjusted manually.
Software Controls: "ALC Enable & Attack Rate (Address 1Ch)" on page 67, "ALC Release Rate (Address 1Dh)" on page 68, "ALC Threshold (Address 1Eh)" on page 69, "ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh)" on page 56.
Input MIN[2:0]
below full scale
MAX[2:0]
below full scale
ALC
PGA Gain and/or Attenuator
ADCx_ATT[7:0] and PGAx_VOL[4:0] volume controls should NOT be adjusted manually when ALCx is enabled.
Output (after ALC) MIN[2:0]
below full scale
MAX[2:0]
below full scale
RRATE[5:0]
ARATE[5:0]
Figure 12. ALC
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4.3.8 Noise Gate
The noise gate may be used to mute signal levels that fall below a programmable threshold. This prevents the ALC from applying gain to noise. A programmable delay may be used to set the minimum time before the noise gate attacks the signal. *Maximum noise gate attenuation levels will depend on the gain applied in either the PGA or MIC preamplifier. For example: If both +32 dB pre-amplification and +12 dB programmable gain is applied, the maximum attenuation that the noise gate achieves will be 52 dB (-96 + 32 + 12) below full-scale. Ramp down time to the maximum setting is affected by the SOFTx bit. Recommended settings: For best results, enable soft ramp for the digital attenuator. When the analog inputs are configured for differential signals (see "Differential Inputs" on page 29), enable the NG_ALL bit to trigger the noise gate only when both inputs fall below the threshold.
Software Controls: "Noise Gate Configuration & Misc. (Address 1Fh)" on page 70, "ADC Control (Address 06h)" on page 52.
Output (dB)
=1 EN G
-52 dB
N
Maximum Attenuation*
N
G
=0 EN
-64 dB
-80 dB
-96 THRESH[2:0]
-40
Input (dB)
Figure 13. Noise Gate Attenuation
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4.4 Analog Outputs
AOUTA and AOUTB are the ground-centered line or headphone outputs. Various signal processing options are available, including digital mixes with the ADC signal and an internal Beep Generator. The desired path to the DAC must be selected using the DATA_SEL[1:0] bits.
Software Controls:
INPUTS FROM ADCA and ADCB
"DAC Control (Address 09h)" on page 55.
SIGNAL PROCESSING ENGINE (SPE)
MUTE_ADCMIXA MUTE_ADCMIXB ADCMIXA_VOL[6:0] ADCMIXB_VOL[6:0] +12dB/-51.5dB 0.5dB steps OUTA_VOL[7:0] OUTB_VOL[7:0] +12dB/-102dB 0.5dB steps
ARATE[7:0] RRATE[7:0] MAX[2:0] MIN[2:0] LIM_SRDIS LIM_ZCDIS LIMIT_EN
VOL PCM Serial Interface
MUTE_PCMMIXA MUTE_PCMMIXB PCMMIXA_VOL[6:0] PCMMIXB_VOL[6:0] +12dB/-51.5dB 0.5dB steps PCMA[1:0] PCMB[1:0] ADCA[1:0] ADCB[1:0]
Chnl Vol. Settings
Channel Swap
TC_EN
Limiter
DEEMPH
Peak Detect
DATA_SEL[1:0]
PDN_DACA PDN_DACB
HP_GAIN[2:0]
Demph
VOL
Channel Swap
VOL
10
VOL
DAC_SZC[1:0] DACA_MUTE DACB_MUTE INV_DACA INV_DACB DAC_SNGVOL AMUTE
Bass/ Treble/ Control
BASS_CF[1:0] TREB_CF[1:0] BASS[3:0] TREB[3:0] +12.0dB/-10.5dB 1.5dB steps
01 00
Switched Capacitor DAC and Filter
Headphone Amp - GND Centered Charge Pump
Left/Right HP Out
BPVOL[4:0] 0dB/-50dB 2.0dB steps
CHRG_FREQ[3:0]
Digital Mix to ADC Serial Interface
OFFTIME[2:0] ONTIME[3:0] FREQ[3:0] REPEAT BEEP
Beep Generator
Figure 14. Output Architecture
4.4.1
De-Emphasis Filter
The CODEC includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter response is shown in Figure 15. The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 s pre-emphasis equalization as a means of noise reduction. De-emphasis is only available in Single Speed Mode.
Software Controls: Hardware Control: "DAC Control (Address 09h)" on page 55. Pin Setting "DEM" pin 4. LO
HI
Gain dB
T1=50 s 0dB
Selection No De-Emphasis De-Emphasis Applied
T2 = 15 s -10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 15. De-Emphasis Curve
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4.4.2 Volume Controls
Three digital volume control functions are implemented, offering independent control over the ADC and PCM signal paths into the mixer as well as a combined control over the mixed signals. All volume controls are programmable to ramp in increments of 0.125 dB at a rate controlled by the DAC soft ramp/zero cross settings. All signal paths may also be independently muted via mute control bits. When enabled, each bit attenuates the signal to its maximum value. When the mute bit is disabled, the signal returns to the attenuation level set in the respective volume control register. The attenuation is ramped up and down at the rate specified by the DAC_SZC[1:0] bits.
Software Controls: "ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh)" on page 58, "PCMX Mixer Volume Control: PCMA (Address 10h) & PCMB (Address 11h)" on page 59, "AOUTx Volume Control: AOUTA (Address 16h) & AOUTB (Address 17h)" on page 64, "DAC Output Control (Address 08h)" on page 54.
4.4.3
Mono Channel Mixer
A channel mixer may be used to create a mix of the left and right channels for either the PCM or ADC signals. This mix allows the user to produce a MONO signal from a stereo source. The mixer may also be used to implement a left/right channel swap.
Software Controls: "ADC & PCM Channel Mixer (Address 18h)" on page 64.
4.4.4
Beep Generator
The Beep Generator generates audio frequencies across approximately two octave major scales. It offers three modes of operation: Continuous, multiple and single (one-shot) beeps. Sixteen on and eight off times are available.
NOTE: The Beep is generated before the limiter and may affect desired limiting performance. If the limiter function is used, it may be required to set the Beep volume sufficiently below the threshold to prevent the peak detect from triggering. Since the master volume control, AOUTx_VOL[7:0], will affect the Beep volume, DAC volume may alternatively be controlled using the PCMMIXx_VOL[6:0] bits.
Software Controls: "Beep Frequency & Timing Configuration (Address 12h)" on page 60, "Beep Off Time & Volume (Address 13h)" on page 61, "Beep Configuration & Tone Configuration (Address 14h)" on page 62
REPEAT = '1' BEEP = '1'
CONTINUOUS BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) and remains on until REPEAT is cleared.
REPEAT = '1' BEEP = '0'
MULTI-BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) for the duration of ONTIME and turns off for the duration of OFFTIME. On and off cycles are repeated until REPEAT is cleared. SINGLE-BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) for the duration of ONTIME. BEEP must be cleared and set for additional beeps.
REPEAT = '0' BEEP = '1'
BPVOL[4:0]
...
FREQ[3:0] ONTIME[3:0] OFFTIME[2:0]
Figure 16. Beep Configuration Options
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4.4.5 Tone Control
Shelving filters are used to implement bass and treble (boost and cut) with four selectable corner frequencies. Boosting will affect peak detect and limiting when levels exceed the maximum threshold settings.
Software Controls: "Tone Control (Address 15h)" on page 63.
4.4.6
Limiter
When enabled, the limiter monitors the digital input signal before the DAC modulator, detects when levels exceed the maximum threshold settings and lowers the AOUT volume at a programmable attack rate below the maximum threshold. When the input signal level falls below the maximum threshold, the AOUT volume returns to its original level set in the Volume Control register at a programmable release rate. Attack and release rates are affected by the DAC soft ramp/zero cross settings and sample rate, Fs. Limiter soft ramp and zero cross dependency may be independently enabled/disabled. Recommended settings: Best limiting performance may be realized with the fastest attack and slowest release setting with soft ramp enabled in the control registers. The "cushion" bits allow the user to set a threshold slightly below the maximum threshold for hysteresis control - this cushions the sound as the limiter attacks and releases. NOTE: When the Limiter is enabled the AOUT Volume is automatically controlled and should not be adjusted manually. Alternative volume control may be realized using the PCMMIXx_VOL[6:0] bits.
Software Controls: "Limiter Release Rate Register (Address 1Ah)" on page 66, "Limiter Attack Rate Register (Address 1Bh)" on page 67, "DAC Control (Address 09h)" on page 55
Input
MAX[2:0]
Limiter
ATTACK/RELEASE SOUND CUSHION
Volume
AOUTx_VOL[7:0] volume control should NOT be adjusted manually when Limiter is enabled.
Output (after Limiter) CUSH[2:0]
MAX[2:0]
ARATE[5:0]
RRATE[5:0]
Figure 17. Peak Detect & Limiter
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4.4.7 Line-Level Outputs and Filtering
The CODEC contains on-chip buffer amplifiers capable of producing line level single-ended outputs on AOUTA and AOUTB. These amplifiers are ground centered and do not have any DC offset. A load stabilizer circuit, shown in the "Typical Connection Diagram (Software Mode)" on page 10 and the "Typical Connection Diagram (Hardware Mode)" on page 11, is required on the analog outputs. This allows the DAC amplifiers to drive line or headphone outputs. Also shown in the Typical Connection diagrams is the recommended passive output filter to support higher impedances such as those found on the inputs to operational amplifiers. "Rext", shown in the typical connection diagrams, is the input impedance of the receiving device. The invert and digital gain controls may be used to provide phase and/or amplitude compensation for an external filter. The delta-sigma conversion process produces high frequency noise beyond the audio passband, most of which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using an off-chip low pass filter.
Software Controls: "DAC Output Control (Address 08h)" on page 54, "AOUTx Volume Control: AOUTA (Address 16h) & AOUTB (Address 17h)" on page 64.
4.4.8
On-Chip Charge Pump
An on-chip charge pump derives a negative supply voltage from the VA_HP supply. This provides dual rail supplies allowing a full-scale output swing centered around ground and eliminates the need for large, DC-blocking capacitors. Added benefits include greater pop suppression and improved low frequency (bass) response. Note: Series resistance in the path of the power supplies must be avoided. Any voltage drop on the VA_HP supply will directly impact the derived negative voltage on the charge pump supply, VSS_HP, and may result in clipping. The FLYN and FLYP pins connect to internal switches that charges and discharges the external capacitor attached, at a default switching frequency. This frequency may be adjusted in the control port registers. Increasing the charge-pumping capacitor will slightly decease the pumping frequency. The capacitor connected to VSS_HP acts as a charge reservoir for the negative supply as well as a filter for the ripple induced by the charge pump. Increasing this capacitor will decrease the ripple on VSS_HP. Refer to the typical connection diagrams in Figure 1 on page 10 or Figure 2 on page 11 for the recommended capacitor values for the charge pump circuitry.
Software Controls: "Charge Pump Frequency (Address 21h)" on page 71.
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4.5 Serial Port Clocking
The CODEC serial audio interface port operates either as a slave or master. It accepts externally generated clocks in slave mode and will generate synchronous clocks derived from an input master clock (MCLK) in master mode. The frequency of the MCLK must be an integer multiple of, and synchronous with, the system sample rate, Fs. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked into or out of the device. The SPEED and MCLKDIV2 software control bits or the SDOUT/(M/S) and MCLKDIV2 stand-alone control pins, configure the device to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode. The value on the SDOUT pin is latched immediately after powering up in hardware mode.
Software Control:
"MIC Power Control & Speed Control (Address 03h)" on page 48, "DAC Control (Address 09h)" on page 55.
Hardware Pin Control: "SDOUT, M/S" pin
29 "MCLKDIV2" pin 2
Setting
47 k Pull-down Slave 47 k Pull-up LO HI Master No Divide
Selection
MCLK is divided by 2 prior to all internal circuitry.
4.5.1
Slave
LRCK and SCLK are inputs in Slave Mode. The speed of the CODEC is automatically determined based on the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will then require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 standalone control pin. Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed mode must be selected using the SPEED[1:0] bits.
Auto-Detect Disabled (Software Mode only) Enabled
QSM 512, 768, 1024, 1536, 2048, 3072
1024, 1536, 2048*, 3072*
HSM 256, 384, 512, 768, 1024, 1536
512, 768, 1024*, 1536*
SSM 128, 192, 256, 384, 512, 768
DSM 128, 192, 256, 384
256, 384, 512*, 768* 128, 192, 256*, 384*
*MCLKDIV2 must be enabled. Table 3. MCLK/LRCK Ratios
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4.5.2 Master
LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled). In hardware mode the CODEC operates in single-speed only. In software mode the CODEC operates in either quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.
/ 128 / 128 / 256 / 512 /1 MCLK /2 1 /2 MCLKDIV2 /2 /4 /8
Double Speed Single Speed Half Speed Quarter Speed Double Speed Single Speed Half Speed Quarter Speed
00 01
LRCK Output (Equal to Fs)
10 11
0 SPEED[1:0]
00 01
SCLK Output
10 11
Figure 18. Master Mode Timing
4.5.3
High-Impedance Digital Output
The serial port may be placed on a clock/data bus that allows multiple masters, without the need for external buffers. The 3ST_SP bit places the internal buffers for the serial port signals in a high-impedance state, allowing another device to transmit clocks or data without bus contention.
CS42L51
Transmitting Device #1
SDOUT
Transmitting Device #2
3ST_SP SCLK/LRCK
Receiving Device
Figure 19. Tri-State Serial Port
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4.5.4 Quarter- and Half-Speed Mode
Quarter-Speed Mode (QSM) and Half-Speed Mode (HSM) allow lower sample rates while maintaining a relatively flat noise floor in the typical audio band of 20 Hz - 20 kHz. Single-Speed Mode (SSM) will allow lower frequency sample rates; however, the DAC's noise floor, that normally rises out-of-band, will scale with the lower sample rate and begin to rise within the audio band. QSM and HSM corrects for most of this scaling, effectively increasing the dynamic range of the CODEC at lower sample rates, relative to SSM.
4.6
Digital Interface Formats
The serial port operates in standard IS, Left-Justified or Right-Justified(DAC only) digital interface formats with varying bit depths from 16 to 24. Data is clocked out of the ADC or into the DAC on the rising edge of SCLK. Figures 20-22 illustrate the general structure of each format. Refer to "Switching Specifications - Serial Port" on page 20 for exact timing relationship between clocks and data.
Software Control:
"Interface Control (Address 04h)" on page 49.
Hardware Pin Control: "IS/LJ" pin 3
Setting
LO HI Left-Justified Interface IS Interface
Selection
LRCK SCLK SDIN SDOUT
MSB
L eft C h a n n el
R ig ht C h a n n el
LS B AOUTA / AINxA
M SB AOUTB / AINxB
LS B
MSB
Figure 20. IS Format
LRCK SCLK SDIN SDOUT
MSB
L eft C h a n n el
R ig ht C h a n n el
LS B AOUTA / AINxA
M SB AOUTB / AINxB
LS B
MSB
Figure 21. Left-Justified Format
LRCK SCLK SDIN
L eft C h a n n el
R ig ht C h a n n el
MSB AOUTA
LSB
M SB AOUTB
LS B
Figure 22. Right-Justified Format (DAC only)
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4.7 Initialization
The initialization and Power-Down sequence flow chart is shown in Figure 23 on page 41. The CODEC enters a Power-Down state upon initial power-up. The interpolation & decimation filters, delta-sigma modulators and control port registers are reset. The internal voltage reference, multi-bit DAC and ADC and switched-capacitor low-pass filters are powered down. The device will remain in the Power-Down state until the RESET pin is brought high. The control port is accessible once RESET is high and the desired register settings can be loaded per the interface descriptions in "Software Mode" on page 42. If a valid write sequence to the control port is not made within approximately 10 ms, the CODEC will enter Hardware Mode. Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage references, DAC_FILT+ and ADC_FILT+, will begin powering up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a muted state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ratio and normal operation begins.
4.8
Recommended Power-Up Sequence
1. Hold RESET low until the power supplies are stable. 2. Bring RESET high. After approximately 10 ms, the device will enter Hardware Mode. 3. For Software Mode operation, set the PDN bit to `1'b in under 10 ms. This will place the device in "standby". 4. Load the desired register settings while keeping the PDN bit set to `1'b. 5. Start MCLK to the appropriate frequency, as discussed in Section 4.5. 6. Set the PDN bit to `0'b. 7. Apply LRCK, SCLK and SDIN for normal operation to begin. 8. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues.
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4.9 Recommended Power-Down Sequence
To minimize audible pops when turning off or placing the CODEC in standby, 1. Mute the DAC's & ADC's. 2. Set the PDN bit in the power control register to `1'b. The CODEC will not power down until it reaches a fully muted sate. 3. Bring RESET low.
No Power 1. No audio signal generated.
Off Mode (Power Applied) 1. No audio signal generated. 2. Control Port Registers reset to default.
PDN bit = '1'b?
Yes
Standby Mode 1. No audio signal generated. 2. Control Port Registers retain settings.
No No RESET = Low? Yes Valid MCLK Applied?
No
20 ms delay Control Port Active Charge Caps 1. VQ Charged to quiescent voltage. 2. Filtx+ Charged.
No
Control Port Valid Write Seq. within 10 ms?
Yes
ADC Initialization 2048 internal MCLK cycle delay
DAC Initialization 50 ms delay
Digital/Analog Output Muted
Charge Pump Powered Up Headphone Amp Powered Down
Power Off Transition 1. Audible pops.
Hardware Mode Minimal feature set support.
Software Mode Registers setup to desired settings.
Sub-Clocks Applied 1. LRCK valid. 2. SCLK valid. 3. Audio samples processed.
20 s delay 20 s delay (DAC only) Headphone Amp Powered Up Stand-By Transition 1. Pops suppressed.
Reset Transition 1. Pops suppressed.
No Valid MCLK/LRCK Ratio? Yes
RESET = Low ERROR: MCLK/LRCK ratio change ERROR: Power removed
Normal Operation Audio signal generated per control port or standalone settings.
PDN bit set to '1'b (software mode only)
ERROR: MCLK removed
Analog Output Freeze 1. Aout bias = last audio sample. 2. DAC Modulators stop operation. 3. Audible pops.
Figure 23. Initialization Flow Chart
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4.10 Software Mode
The control port is used to access the registers allowing the CODEC to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port operates in 2 modes: SPI and IC, with the CODEC acting as a slave device. SPI mode is selected if there is a high-to-low transition on the AD0/CS pin after the RESET pin has been brought high. IC mode is selected by connecting the AD0/CS pin through a resistor to VL or DGND, thereby permanently selecting the desired AD0 bit address state.
4.10.1 SPI Control
In SPI mode, CS is the CS42L51 chip select signal, CCLK is the control port bit clock (input into the CS42L51 from the microcontroller), CDIN is the input data line from the microcontroller. Data is clocked in on the rising edge of CCLK. The CODEC will only support write operations. Read request will be ignored. Figure 24 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be 1001010. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data which will be placed into the register designated by the MAP. There is MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will autoincrement after each byte is read or written, allowing block reads or writes of successive registers.
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CCLK
CHIP ADDRESS (WRITE) MAP BYTE
0
INCR
DATA
2 1 0 7 6 1 0 7
DATA +n
6 1 0
CDIN
1
0
0
1
0
1
0
6
5
4
3
Figure 24. Control Port Timing in SPI Mode
4.10.2 IC Control
In IC mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no CS pin. Pin AD0 forms the least significant bit of the chip address and should be connected through a resistor to VL or DGND as desired. The state of the pin is sensed while the CS42L51 is being reset. The signal timings for a read and write cycle are shown in Figure 25 and Figure 26. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS42L51 after a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low for a write). The upper 6 bits of the 7-bit address field are fixed at 100101. To communicate with a CS42L51, the chip address field, which is the first byte sent to the CS42L51, should match 100101 followed by the setting of the AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read,
42
DS679A2
CS42L51
the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS42L51 after each input byte is read, and is input to the CS42L51 from the microcontroller after each transmitted byte.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19
24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
0
INCR
DATA
2 1 0 7 6 1 0 7
DATA +1
6 1 0 7
DATA +n
6 1 0
SDA
1
0
0
1
0
1
AD0
6
5
4
3
ACK START
ACK
ACK
ACK STOP
Figure 25. Control Port Timing, IC Write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
STOP
1 0 1
CHIP ADDRESS (READ)
0 0 1 0 1 AD0 1
DATA
7 0
DATA +1
7 0
DATA + n
7 0
SDA
1
0
0
1
0 1 AD0 0
6
5
4
3
2
ACK START
ACK START
ACK
ACK
NO ACK
STOP
Figure 26. Control Port Timing, IC Read
Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As shown in Figure 26, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send start condition. Send 100101x0 (chip address & write operation). Receive acknowledge bit. Send MAP byte, auto increment off. Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 100101x1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit.
DS679A2
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CS42L51
4.10.3 Memory Address Pointer (MAP)
The MAP byte comes after the address byte and selects the register to be read or written. Refer to the pseudo code above for implementation details.
4.10.3.1 Map Increment (INCR)
The device has MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive IC writes or reads and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of successive registers.
44
DS679A2
CS42L51 5. REGISTER QUICK REFERENCE
Software Mode register defaults are as shown. "Reserved" registers must maintain their default state.
Addr
01h 02h 03h
Function
ID. p 47. default Power Ctl. 1. p 47. default Speed Ctl. & Power Ctl. 2. p 48. default Interface Ctl. p 49. default MIC Control & Misc. p 51. default ADC Control. p 52. default
7
Chip_ID4 1 Reserved 0 AUTO 1 SDOUT->SDIN 0 ADC_SNGVOL 0 ADCB_HPF EN 1 AINB_MUX1
6
Chip_ID3 1 0 SPEED1 0 M/S 0 ADCB_ DBOOST 0 ADCB_HP FRZ 0
5
Chip_ID2 0 0 SPEED0 1 DAC_DIF2 0 ADCA_ DBOOST 0 ADCA_HPF EN 1
4
Chip_ID1 1 PDN_PGAB 0 3-ST_SP 0 DAC_DIF1 0 MICBIAS_ SEL 0 ADCA_HP FRZ 0
3
Chip_ID0 1 PDN_PGAA 0 PDN_MICB 1 DAC_DIF0 0 MICBIAS_ LVL1 0 SOFTB 0 INV_ADCB
2
Rev_ID2 0 PDN_ADCB 0 PDN_MICA 1 ADC_IS/LJ 0 MICBIAS_ LVL0 0 ZCROSSB 0 INV_ADCA
1
Rev_ID1 0 PDN_ADCA 0 PDN_ MICBIAS 1 DIGMIX 0 MICB_ BOOST 0 SOFTA 0 ADCB_ MUTE 0 DACB_ MUTE 0 DAC_SZC1 1 PGAA VOL1 0 PGAB VOL1 0
0
Rev_ID0 0 PDN 0 MCLKDIV2 0 MICMIX 0 MICA_ BOOST 0 ZCROSSA 0 ADCA_ MUTE 0 DACA_ MUTE 0 DAC_SZC0 0 PGAA VOL0 0 PGAB VOL0 0
PDN_DACB PDN_DACA
04h 05h
06h
07h
ADC Input Select. , Invert, Mute. p 53. default DAC Output Control. p 54. default DAC Control. p 55. default ALCA SZC & PGAA Volume. p 56. default ALCB SZC & PGAB Volume . p 56. default
AINB_MUX AINA_MUX1 AINA_MUX0 0 0 HP_GAIN1 1 DATA_SEL0 0 ALCA_ZC DIS 0 ALCB_ZC DIS 0 0 HP_GAIN0 1 FREEZE 0 Reserved 0 DAC_SNG VOL 0 Reserved 0 PGAA VOL4 0 PGAB VOL4 0
0 HP_GAIN2 0 DATA_SEL1 0 ALCA_SR DIS 0 ALCB_SR DIS 0 ADCA_ATT7 0 ADCB_ATT7 0 MUTE_ADC MIXA 1 MUTE_ADC MIXB 1 MUTE_PCM MIXA 1 MUTE_PCM MIXB 1
0 INV_DACB 0 DEEMPH 0 PGAA VOL3 0 PGAB VOL3 0
0 INV_DACA 0 Reserved 1 PGAA VOL2 0 PGAB VOL2 0
08h
09h 0Ah
0 Reserved
0Bh
0
0Ch ADCA Attenuator. p 57. default 0Dh ADCB Attenuator . p 57. default 0Eh Vol. Control ADCMIXA. p 58. default 0Fh Vol. Control ADCMIXB. p 58. default 10h Vol. Control PCMMIXA. p 59. default 11h Vol. Control PCMMIXB. p 59. default
ADCA_ATT ADCA_ATT5 ADCA_ATT4 ADCA_ATT3 ADCA_ATT2 ADCA_ATT1 ADCA_ATT0 6 0 0 0 0 0 0 0 ADCB_ATT ADCB_ATT5 ADCB_ATT4 ADCB_ATT3 ADCB_ATT2 ADCB_ATT1 ADCB_ATT0 6 0 ADCMIXA VOL6 0 ADCMIXB VOL6 0 PCMMIXA VOL6 0 PCMMIXB VOL6 0 0 ADCMIXA VOL5 0 ADCMIXB VOL5 0 PCMMIXA VOL5 0 PCMMIXB VOL5 0 0 ADCMIXA VOL4 0 ADCMIXB VOL4 0 PCMMIXA VOL4 0 PCMMIXB VOL4 0 0 ADCMIXA VOL3 0 ADCMIXB VOL3 0 PCMMIXA VOL3 0 PCMMIXB VOL3 0 0 ADCMIXA VOL2 0 ADCMIXB VOL2 0 PCMMIXA VOL2 0 PCMMIXB VOL2 0 0 ADCMIXA VOL1 0 ADCMIXB VOL1 0 PCMMIXA VOL1 0 PCMMIXB VOL1 0 0 ADCMIXA VOL0 0 ADCMIXB VOL0 0 PCMMIXA VOL0 0 PCMMIXB VOL0 0
DS679A2
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CS42L51
Addr
12h
Function
BEEP Freq. & OnTime . p 60. default BEEP Off Time & Vol. p 61. default BEEP Control & Tone Config. p 62. default Tone Control. p 63. default Vol. Control AOUTA. p 64. default Vol. Control AOUTB. p 64. default PCM & ADC Channel Mixer. p 64. default Limiter Threshold & SZC Disable. p 65. default Limiter Config & Release Rate. p 66. default Limiter Attack Rate. p 67. default
7
FREQ3 0 OFFTIME2 0 REPEAT
6
FREQ2 0 OFFTIME1 0 BEEP
5
FREQ1 0 OFFTIME0 0 Reserved
4
FREQ0 0 BPVOL4 0 TREB_CF1
3
ONTIME3 0 BPVOL3 0 TREB_CF0
2
ONTIME2 0 BPVOL2 0 BASS_CF1
1
ONTIME1 0 BPVOL1 0 BASS_CF0
0
ONTIME0 0 BPVOL0 0 TC_EN
13h
14h
0 TREB3 1 AOUTA_ VOL7 0 AOUTB_ VOL7 0 PCMA1
0 TREB2 0 AOUTA_ VOL6 0 AOUTB_ VOL6 0 PCMA0
0 TREB1 0 AOUTA_ VOL5 0 AOUTB_ VOL5 0 PCMB1
0 TREB0 0 AOUTA_ VOL4 0 AOUTB_ VOL4 0 PCMB0
0 BASS3 1 AOUTA_ VOL3 0 AOUTB_ VOL3 0 ADCA1
0 BASS2 0 AOUTA_ VOL2 0 AOUTB_ VOL2 0 ADCA0
0 BASS1 0 AOUTA_ VOL1 0 AOUTB_ VOL1 0 ADCB1
0 BASS0 0 AOUTA_ VOL0 0 AOUTB_ VOL0 0 ADCB0
15h 16h
17h
18h
0 MAX2
0 MAX1
0 MAX0
0 CUSH2
0 CUSH1
0 CUSH0
0 LIM_SRDIS
0 LIM_ZCDIS
19h
0 LIMIT_EN
0 LIMIT_ALL
0 LIM_RRATE 5 0
0 LIM_RRATE 4 0
0 LIM_RRATE 3 0
0 LIM_RRATE 2 0
0 LIM_RRATE 1 0
0 LIM_RRATE 0 0
1Ah
0 Reserved 0 ALC_ENB
1 Reserved 0 ALC_ENA
1Bh
LIM_ARATE5 LIM_ARATE4 LIM_ARATE3 LIM_ARATE2 LIM_ARATE1 LIM_ARATE0 0 0 0 0 0 0
1Ch ALC Enable & Attack Rate. p 67. default 1Dh ALC Release Rate. p 68. default 1Eh ALC Threshold. p 69. default 1Fh Noise Gate Config. p 70. default 20h Status. p 71. default 21h
ALC_ARATE AALC_RATE ALC_ARATE ALC_ARATE ALC_ARATE ALC_ARATE 2 1 0 5 4 3 0 0 0 0 0 0
0 Reserved 0 MAX2 0 NG_ALL 0 Reserved 0
0 Reserved 0 MAX1 0 NG_EN 0
ALC_RRATE ALC_RRATE ALC_RRATE ALC_RRATE ALC_RRATE ALC_RRATE 5 4 3 2 1 0 0 MAX0 0 NG_BOOST 0 0 MIN2 0 THRESH2 0 0 MIN1 0 THRESH1 0 0 MIN0 0 THRESH0 0 0 Reserved 0 NGDELAY1 0 0 Reserved 0 NGDELAY0 0
SP_CLKER SPEB_OVFL SPEA_OVFL PCMA_OVFL PCMB_OVFL ADCA_OVFL ADCB_OVFL R 0 CHRG_ FREQ2 1 0 CHRG_ FREQ1 0 0 CHRG_ FREQ0 1 0 Reserved 0 0 Reserved 0 0 Reserved 0 0 Reserved 0
Charge Pump CHRG_FREQ3 Frequency. p 71. default 0
46
DS679A2
CS42L51 6. REGISTER DESCRIPTION
All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description. All "Reserved" registers must maintain their default state.
Note:
Certain functions are only available when the "Signal Processing Engine to DAC" option is selected using the DATA_SEL[1:0] bits, as described in section "DAC Data Selection (DATA_SEL[1:0])" on page 55.
6.1
Chip I.D. and Revision Register (Address 01h) (Read Only)
6 Chip_ID3 5 Chip_ID2 4 Chip_ID1 3 Chip_ID0 2 Rev_ID2 1 Rev_ID1 0 Rev_ID0
7 Chip_ID4
Chip I.D. (Chip_ID[4:0])
Default: 11011 Function: I.D. code for the CS42L51. Permanently set to 11011.
Chip Revision (Rev_ID[2:0])
Default: 000 Function: CS42L51 revision level. Revision A is coded as 000.
6.2
Power Control 1 (Address 02h)
6 PDN_DACB 5 PDN_DACA 4 PDN_PGAB 3 PDN_PGAA 2 PDN_ADCB 1 PDN_ADCA 0 PDN
7 Reserved
Notes:
1. To activate the power down sequence for individual channels (A or B) both channels must first be powered down either by enabling the PDN bit or by enabling the power down bits for both channels. Enabling the power down bit on an individual channel basis after the CODEC has fully powered up, will mute the selected channel without achieving any power savings. Recommended channel power down sequence: (1) Enable the PDN bit, (2) enable power down for the select channels, (2) disable the PDN bit.
Power Down DAC X (PDN_DACX)
Default: 0 0 - Disable 1 - Enable Function: DAC channel x will either enter a power down or muted state when this bit is enabled. See Note 1 above.
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CS42L51
Power Down PGA X (PDN_PGAX)
Default: 0 0 - Disable 1 - Enable Function: PGA channel x will either enter a power down or muted state when this bit is enabled. See note 1 on page 47. This bit is used in conjunction with AINx_MUX bits to determine the analog input path to the ADC. Refer to "ADCX Input Select Bits (AINX_MUX[1:0])" on page 53 for the required settings.
Power Down ADC X (PDN_ADCX)
Default: 0 0 - Disable 1 - Enable Function: ADC channel x will either enter a power down or muted state when this bit is enabled. See note 1 on page 47.
Power Down (PDN)
Default: 0 0 - Disable 1 - Enable Function: The entire CODEC will enter a low-power state when this function is enabled. The contents of the control port registers are retained in this mode.
6.3
MIC Power Control & Speed Control (Address 03h)
7 AUTO 6 SPEED1 5 SPEED0 4 3-ST_SP 3 PDN_MICB 2 PDN_MICA 1 PDN_MICBIAS 0 MCLKDIV2
Auto-Detect Speed Mode (AUTO)
Default: 1 0 - Disable 1 - Enable Function: Enables the auto-detect circuitry for detecting the speed mode of the CODEC when operating as a slave. When AUTO is enabled, the MCLK/LRCK ratio must be implemented according to Table 3 on page 37. The SPEED[1:0] bits are ignored when this bit is enabled. Speed is determined by the MCLK/LRCK ratio.
Speed Mode (SPEED[1:0])
Default: 01 11 - Quarter-Speed Mode (QSM) - 4 to 12.5 kHz sample rates 10 - Half-Speed Mode (HSM) - 12.5 to 25 kHz sample rates 01 - Single-Speed Mode (SSM) - 4 to 50 kHz sample rates 00 - Double-Speed Mode (DSM) - 50 to 100 kHz sample rates Function: Sets the appropriate speed mode for the CODEC in master or slave mode. QSM is optimized for 8 kHz sample rate and HSM is optimized for 16 kHz sample rate. These bits are ignored when the AUTO bit is enabled (see Auto-Detect Speed Mode (AUTO) above).
48
DS679A2
CS42L51
Tri-State Serial Port Interface (3ST_SP)
Default: 0 0 - Disable 1 - Enable Function: When enabled, and the device is configured as a master, then all Serial Port interface signals will be placed in a high-impedance output state. If the serial port interface is configured as a slave, only the SDOUT pin will be placed in a high-impedance state. The other signals will remain as inputs.
Power Down MIC X (PDN_MICX)
Default: 1 0 - Disable 1 - Enable Function: When enabled, the microphone pre-amplifier for channel x will be in a power down state.
Power Down MIC BIAS (PDN_MICBIAS)
Default: 1 0 - Disable 1 - Enable Function: When enabled, the microphone bias circuit will be in a power down state.
MCLK Divide By 2 (MCLKDIV2)
Default: 0 0 - Disabled 1 - Divide by 2 Function: Divides the input MCLK by 2 prior to all internal circuitry. This bit is ignored when the AUTO bit is disabled in slave mode.
6.4
Interface Control (Address 04h)
6 M/S 5 DAC_DIF2 4 DAC_DIF1 3 DAC_DIF0 2 ADC_IS/LJ 1 DIGMIX 0 MICMIX
7 SDOUT->SDIN
SDOUT to SDIN Loopback (SDOUT->SDIN)
Default: 0 0 - Disabled; SDOUT internally disconnected from SDIN 1 - Enabled; SDOUT internally connected to SDIN Function: Internally loops the signal on the SDOUT pin to SDIN.
Master/Slave Mode (M/S)
Default: 0 0 - Slave 1 - Master Function: Selects either master or slave operation for the serial port.
DS679A2
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CS42L51
DAC Digital Interface Format (DAC_DIF[2:0])
Default = 000
DAC_DIF[2:0] 000 001 010 011 100 101 110 100
Description Left Justified, up to 24-bit data IS, up to 24-bit data Right Justified, 24-bit data Right Justified, 20-bit data Right Justified, 18-bit data Right Justified, 16-bit data Reserved Reserved
Figure 21 on page 39 20 on page 39 22 on page 39 22 on page 39 22 on page 39 22 on page 39 -
Function: Selects the digital interface format used for the data in on SDIN. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in the section "Digital Interface Formats" on page 39.
ADC IS or Left-Justified (ADC_IS/LJ)
Default: 0 0 - Left-Justified 1 - IS Function: Selects either the IS or Left-Justified digital interface format for the data on SDOUT. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in the section "Digital Interface Formats" on page 39.
Digital Mix (DIGMIX)
Default: 0
DIGMIX 0
1
DATA_SEL[1:0] xx 00 01 10 11
Mix Selected No Mix: ADC to ADC serial port, SDOUT data. No Mix: SDIN data to ADC serial port, SDOUT data. Mix: ADC + SDIN data to ADC serial port, SDOUT data. No Mix: ADC to ADC serial port, SDOUT data. Reserved
Function: Selects between the ADC or a digital mix of the ADC and DAC into the serial port to the SDOUT pin. This mix function is affected by the data select bits DATA_SEL[1:0].
Microphone Mix (MICMIX)
Default: 0 0 - Disabled; No Mix: Left/Right Channel to ADC serial port, SDOUT. 1 - Enabled; Mix: Differential mix ((A-B)/2)to ADC serial port, SDOUT. Function: Selects between the ADC stereo mix or a differential mix of analog inputs A and B.
50
DS679A2
CS42L51
6.5
7
MIC Control (Address 05h)
6 5 4 3 2 1
MICB_BOOST
0
MICA_BOOST
ADC_SNGVOL ADCB_DBOOST ADCA_DBOOST MICBIAS_SEL
MICBIAS_LVL1 MICBIAS_LVL0
ADC Single Volume Control (ADC_SNGVOL)
Default: 0 0 - Disabled 1 - Enabled Function: The individual PGA Volume (PGAx_VOLx) and ADC channel attenuation (ADCx_ATTx) levels are independently controlled by their respective control registers when this function is disabled. When enabled, the volume on both channels is determined by the ADCA Attenuator Control register, or the PGAA Control register, and the ADCB Attenuator and PGAB Control registers are ignored.
ADCx 20dB Digital Boost (ADCx_DBOOST)
Default: 0 0 - Disabled 1 - Enabled Function: Applies a 20dB digital gain to the input signal on ADC channel x, regardless of the input path.
MIC Bias Select (MICBIAS_SEL)
Default: 0 0 - MICBIAS on AIN3B/MICIN2 pin 1 - MICBIAS on AIN2B pin Function: Determines the output pin for the internally generated MICBIAS signal. If set to `0'b, then the MICBIAS is output on the AIN3B/MICIN2 pin. If set to `1'b, then the MICBIAS is output on the AIN2B pin.
MIC Bias Level (MICBIAS_LVL[1:0])
Default: 00 00 - 0.8 x VA 01 - 0.7 x VA 10 - 0.6 x VA 11 - 0.5 x VA Function: Determines the output voltage level of the MICBIAS output.
MIC X Preamplifier Boost (MICX_BOOST)
Default: 0 0 - +16 dB Gain 1 - +32 dB Gain Function: Determines the amount of gain applied to the microphone preamplifier for channel x.
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CS42L51
6.6 ADC Control (Address 06h)
3 SOFTB 2 ZCROSSB 1 SOFTA 0 ZCROSSA 7 6 5 4 ADCB_HPFEN ADCB_HPFRZ ADCA_HPFEN ADCA_HPFRZ
ADCX High-Pass Filter Enable (ADCX_HPFEN)
Default: 1 0 - High-pass filter is disabled 1 - High-pass filter is enabled Function: When this bit is set, the internal high-pass filter will be enabled for ADCx. When set to `0', the high-pass filter will be disabled. For DC measurements, this bit must be cleared to `0'. See "ADC Digital Filter Characteristics" on page 15.
ADCX High-Pass Filter Freeze (ADCX_HPFRZ)
Default: 0 0 - Continuous DC Subtraction 1 - Frozen DC Subtraction Function: The high-pass filter works by continuously subtracting a measure of the DC offset from the output of the decimation filter. If the ADCx_HPFRZ bit is taken high during normal operation, the current value of the DC offset is frozen and this DC offset will continue to be subtracted from the conversion result. For DC measurements, this bit must be set to `1'. See "ADC Digital Filter Characteristics" on page 15.
Soft Ramp CHX Control (SOFTX)
Default: 0 0 - Disabled 1 - Enabled Function: Soft Ramp allows level changes to be implemented via an incremental ramp. ADCx_ATT[7:0] digital attenuation changes are ramped from the current level to the new level at a rate of 0.125 dB per LRCK period. PGAx_VOL[4:0] gain changes are ramped in 0.5 dB steps every 16 LRCK periods. Soft Ramp & Zero Cross Enabled When used in conjunction with the ZCROSSx bit, the PGAx_VOL[4:0] gain changes will occur in 0.5 dB steps and be implemented on a signal zero crossing.
Zero Cross CHX Control (ZCROSSX)
Default: 0 0 - Disabled 1 - Enabled Function: Zero Cross Enable dictates that signal level changes will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period of 1024 sample periods (approximately 10.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp & Zero Cross Enabled When used in conjunction with the SOFTx bit, the PGAx_VOL[4:0] gain changes will occur in 0.5 dB steps and be implemented on a signal zero crossing. The ADC Attenuator ADCx_ATT[7:0] is not affected by the ZCROSSx bit.
52
DS679A2
CS42L51
SOFTx
0 0 1 1
ZCROSSx
0 1 0 1
Analog PGA Volume (PGAx_VOL[4:0])
Volume changes immediately. Volume changes at next zero cross time. Volume changes in 0.5 dB steps. Volume changes in 0.5 dB steps at every signal zero-cross.
Digital Attenuator (ADCx_ATT[7:0])
Volume changes immediately. Volume changes immediately. Change volume in 0.125 dB steps. Change volume in 0.125 dB steps.
6.7
ADCx Input Select, Invert & Mute (Address 07h)
6 AINB_MUX0 5 AINA_MUX1 4 AINA_MUX0 3 INV_ADCB 2 INV_ADCA 1 0 ADCB_MUTE ADCA_MUTE
7 AINB_MUX1
ADCX Input Select Bits (AINX_MUX[1:0])
Default: 00
PDN_PGAx
0 0 0 0 1 1 1 1
AINx_MUX[1:0]
00 01 10 11 00 01 10 11
Selected Path to ADC AIN1x-->PGAx AIN2x-->PGAx AIN3x/MICINx-->PGAx AIN3x/MICINx-->Pre-Amp(+16/+32 dB Gain)-->PGAx AIN1x AIN2x AIN3x/MICINx Reserved
Function: Selects the specified analog input signal into ADCx. The microphone pre-amplifier is only available when PDN_PGAx is disabled. See Figure 27.
AIN1x AIN2x AIN1x AIN2x AIN3x
MUX
ADC
MUX
+16/ 32 dB
PGA
AIN3x / MICINx
Decoder
AINx_MUX[1:0] PDN_PGAx
Figure 27. AIN & PGA Selection
DS679A2
53
CS42L51
ADCX Invert Signal Polarity (INV_ADCX)
Default: 0 0 - Disabled 1 - Enabled Function: When enabled, this bit will invert the signal polarity of the ADC x channel.
ADCX Channel Mute (ADCX_MUTE)
Default: 0 0 - Disabled 1 - Enabled Function: The output of channel x ADC will mute when enabled. The muting function is affected by the ADCx Soft bit (SOFT).
6.8
DAC Output Control (Address 08h)
6 HP_GAIN1 5 HP_GAIN0 4 DAC_SNGVO L 3 INV_PCMB 2 INV_PCMA 1 0 DACB_MUTE DACA_MUTE
7 HP_GAIN2
Headphone Analog Gain (HP_GAIN[2:0])
Default: 011
HP_GAIN[2:0] 000 001 010 011 100 101 110 111
Gain Setting 0.3959 0.4571 0.5111 0.6047 0.7099 0.8399 1.000 1.1430
Function: These bits select the gain multiplier for the headphone/line outputs. See "Line Output Voltage Characteristics" on page 18 and "Headphone Output Power Characteristics" on page 19.
DAC Single Volume Control (DAC_SNGVOL)
Default: 0 Function: The individual channel volume levels are independently controlled by their respective Volume Control registers when this function is disabled. When enabled, the volume on all channels is determined by the AOUTA Volume Control register and the AOUTB Volume Control register is ignored.
54
DS679A2
CS42L51
PCMX Invert Signal Polarity (INV_PCMX)
Default: 0 0 - Disabled 1 - Enabled Function: When enabled, this bit will invert the signal polarity of the PCM x channel.
DACX Channel Mute (DACX_MUTE)
Default: 0 0 - Disabled 1 - Enabled Function: The output of channel x DAC will mute when enabled. The muting function is affected by the DACx Soft and Zero Cross bits (DACx_SZC[1:0]).
6.9
DAC Control (Address 09h)
6 DATA_SEL0 5 FREEZE 4 Reserved 3 DEEMPH 2 Reserved 1 DAC_SZC1 0 DAC_SZC0
7 DATA_SEL1
DAC Data Selection (DATA_SEL[1:0])
Default: 00 00 - PCM Serial Port to DAC 01 - Signal Processing Engine to DAC 10 - ADC Serial Port to DAC 11 - Reserved Function: Selects the digital signal source for the DAC. NOTE: Certain functions are only available when the "Signal Processing Engine to DAC" option is selected using these bits.
Freeze Controls (FREEZE)
Default: 0 Function: This function will freeze the previous settings of, and allow modifications to be made to all control port registers without the changes taking effect until the FREEZE is disabled. To have multiple changes in the control port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
DAC De-Emphasis Control (DEEMPH)
Default: 0 0 - No De-Emphasis 1 - De-Emphasis Enabled Function: NOTE: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control. Enables the digital filter to apply the standard 15s/50s digital de-emphasis filter response for a sample rate of 44.1 kHz.
DS679A2
55
CS42L51
DAC Soft Ramp and Zero Cross Control (DAC_SZC[1:0])
Default = 01 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: NOTE: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control Immediate Change When Immediate Change is selected all volume level changes will take effect immediately in one step. Zero Cross This setting dictates that signal level changes, either by gain changes, attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. NOTE: The LIM_SRDIS bit is ignored. Soft Ramp Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 0.5 dB per 4 left/right clock periods. Soft Ramp on Zero Crossing This setting dictates that signal level changes, either by gain changes, attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. NOTE: The LIM_SRDIS bit is ignored.
6.10
ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh)
5 Reserved 4 PGAX_VOL4 3 PGAX_VOL3 2 PGAX_VOL2 1 PGAX_VOL1 0 PGAX_VOL0
7 6 ALCX_SRDIS ALCX_ZCDIS
ALCX Soft Ramp Disable (ALCX_SRDIS)
Default: 0 0 - Off 1 - On Function: Overrides the SOFTx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not be dictated by the soft ramp setting. ALC volume level changes will take effect in one step.
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ALCX Zero Cross Disable (ALCX_ZCDIS)
Default: 0 0 - Off 1 - On Function: Overrides the ZCROSSx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not be dictated by the zero cross setting. ALC volume level changes will take effect immediately in one step.
PGA X Gain Control (PGAX_VOL[4:0])
Default: 00000
Binary Code 11000 *** 01010 *** 00000 11111 11110 *** 11010
Volume Setting +12 dB *** +5 dB *** 0 dB -0.5 dB -1 dB *** -3 dB
Function: The PGAx Gain Control register allows independent setting of the signal levels in 0.5 dB increments as dictated by the ADCx Soft and Zero Cross bits (SOFTx & ZCROSSx) from +12 dB to -3 dB. Gain settings are decoded as shown in the table above. The gain changes are implemented as dictated by the ALCX Soft & Zero Cross bits (ALCX_SZC). Levels are decoded as described in the table above.
Note:
When the ALC is enabled the PGA is automatically controlled and should not be adjusted manually.
6.11
ADCx Attenuator: ADCA (Address 0Ch) & ADCB (Address 0Dh)
6 ADCx_ATT6 5 ADCx_ATT5 4 ADCx_ATT4 3 ADCx_ATT3 2 ADCx_ATT2 1 ADCx_ATT1 0 ADCx_ATT0
7 ADCx_ATT7
ADCX Attenuation Control (ADCX_ATT[7:0])
Default: 00h
Binary Code 0111 1111 *** 0000 0000 1111 1111 1111 1110 *** 1010 0000 *** 1000 0000
Volume Setting 0 dB *** 0 dB -1 dB -2 dB *** -96 dB *** -96 dB
Function: The level of ADCX can be adjusted in 1.0 dB increments as dictated by the ADCx Soft and Zero Cross bits
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(SOFTx & ZCROSSx) from 0 to -96 dB. Levels are decoded in two's complement, as shown in the table above.
Note:
When the ALC is enabled the Attenuator and PGA volume is automatically controlled and should not be adjusted manually.
6.12
7
ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh)
6 5 4 3 2 1 0
MUTE_ADCMIXx ADCMIXx_VOL6 ADCMIXx_VOL5 ADCMIXx_VOL4 ADCMIXx_VOL3 ADCMIXx_VOL2 ADCMIXx_VOL1 ADCMIXx_VOL0
NOTE: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. ADCX Mixer Channel Mute (MUTE_ADCMIXX)
Default: 1 0 - Disabled 1 - Enabled Function: The ADC channel X input to the output mixer will mute when enabled. The muting function is affected by the DACX Soft and Zero Cross bits (DACX_SZC[1:0]).
ADCX Mixer Volume Control (ADCMIXX_VOL[6:0])
Default = 000 0000
Binary Code 001 1000 *** 000 0000 111 1111 111 1110 *** 001 1001
Volume Setting +12.0 dB *** 0 dB -0.5 dB -1.0 dB *** -51.5 dB
Function: The level of the ADCX input to the output mixer can be adjusted in 0.5 dB increments as dictated by the DACX Soft and Zero Cross bits (DACX_SZC[1:0]) from +12 to -51.5 dB. Levels are decoded as shown in the table above.
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6.13
7
PCMX Mixer Volume Control: PCMA (Address 10h) & PCMB (Address 11h)
6 5 4 3 2 1 0
MUTE_PCMMIXx PCMMIXx_VOL PCMMIXx_VOL PCMMIXx_VOL PCMMIXx_VOL PCMMIXx_VOL PCMMIXx_VOL PCMMIXx_VOL 6 5 4 3 2 1 0
NOTE: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. PCMX Mixer Channel Mute (MUTE_PCMMIXX)
Default = 1 0 - Disabled 1 - Enabled Function: The PCM channel X input to the output mixer will mute when enabled. The muting function is affected by the DACX Soft and Zero Cross bits (DACX_SZC[1:0]).
PCMX Mixer Volume Control (PCMMIXX_VOL[6:0])
Default: 000 0000
Binary Code 001 1000 *** 000 0000 111 1111 111 1110 *** 001 1001
Volume Setting +12.0 dB *** 0 dB -0.5 dB -1.0 dB *** -51.5 dB
Function: The level of the PCMX input to the output mixer can be adjusted in 0.5 dB increments as dictated by the DACX Soft and Zero Cross bits (DACX_SZC[1:0]) from +12 to -51.5 dB. Levels are decoded as described in the table above.
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6.14 Beep Frequency & Timing Configuration (Address 12h)
6 FREQ2 5 FREQ1 4 FREQ0 3 ONTIME3 2 ONTIME2 1 ONTIME1 0 ONTIME0 7 FREQ3
NOTE: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Beep Frequency (FREQ[3:0])
Default: 0000
FREQ[3:0]
Frequency Pitch Fs = 12, 24, 48 or 96 kHz
260.87 Hz 521.74 Hz 585.37 Hz 666.67 Hz 705.88 Hz 774.19 Hz 888.89 Hz 1000.00 Hz 1043.48 Hz 1200.00 Hz 1333.33 Hz 1411.76 Hz 1600.00 Hz 1714.29 Hz 2000.00 Hz 2181.82 Hz C4 C5 D5 E5 F5 G5 A5 B5 C6 D6 E6 F6 G6 A6 B6 C7
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Function: The frequency of the beep signal can be adjusted from 260.87 Hz to 2181.82 Hz. Beep frequency will scale directly with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to Figure 16 on page 34 for single, multiple and continuous beep configurations using the REPEAT and BEEP bits.
Beep On Time Duration (ONTIME[3:0])
Default: 00h
TIME[3:0]
0000
***
1111
On Time Fs = 12, 24, 48 or 96 kHz 86 ms *** 5.2 s
Function: The on-duration of the beep signal can be adjusted from approximately 86 ms to 5.2 s. The on-duration will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to Figure 16 on page 34 for single, multiple and continuous beep configurations using the REPEAT and BEEP bits.
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6.15 Beep Off Time & Volume (Address 13h)
6 OFFTIME1 5 OFFTIME0 4 BPVOL4 3 BPVOL3 2 BPVOL2 1 BPVOL1 0 BPVOL0 7 OFFTIME2
NOTE: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Beep Off Time (OFFTIME[2:0])
Default: 0
OFFTIME[2:0]
000 001 010 011 100 101 110 111
Off Time Fs = 12, 24, 48 or 96 kHz 1.23 s 2.58 s 3.90 s 5.20 s 6.60 s 8.05 s 9.35 s 10.80 s
Function: The off-duration of the beep signal can be adjusted from approximately 75 ms to 680 ms. The off-duration will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to Figure 16 on page 34 for single, multiple and continuous beep configurations using the REPEAT and BEEP bits.
Beep Volume (BPVOL[4:0])
Default: 00000
Binary Code 00110 *** 00000 11111 11110 *** 00111
Volume Setting +12.0 dB *** 0 dB -2 dB -4 dB *** -50 dB
Function: The level of the Beep into the output mixer can be adjusted in 2.0 dB increments from +12 dB to -50 dB. Refer to Figure 16 on page 34 for single, multiple and continuous beep configurations using the REPEAT and BEEP bits. Levels are decoded as described in the table above.
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6.16 Beep Configuration & Tone Configuration (Address 14h)
6 BEEP 5 Reserved 4 TREB_CF1 3 TREB_CF0 2 BASS_CF1 1 BASS_CF0 0 TC_EN 7 REPEAT
NOTE: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Repeat Beep (REPEAT)
Default: 0 0 - Disabled 1 - Enabled Function: This bit is used in conjunction with the BEEP bit to mix a continuous or periodic beep with the analog output. Refer to Figure 16 on page 34 for a description of each configuration option.
Beep (BEEP)
Default: 0 0 - Disabled 1 - Enabled Function: This bit is used in conjunction with the REPEAT bit to mix a continuous or periodic beep with the analog output. Note: Re-engaging the beep before it has completed its initial cycle will cause the beep signal to remain ON for the maximum ONTIME duration. Refer to Figure 16 on page 34 for a description of each configuration option.
Treble Corner Frequency (TREB_CF[1:0])
Default: 00 00 - 5 kHz 01 - 7 kHz 10 - 10 kHz 11 - 15 kHz Function: The treble corner frequency is user selectable as shown above.
Bass Corner Frequency (BASS_CF[1:0])
Default: 00 00 - 50 Hz 01 - 100 Hz 10 - 200 Hz 11 - 250 Hz Function: The bass corner frequency is user selectable as shown above.
Tone Control Enable (TC_EN)
Default = 0 0 - Disabled 1 - Enabled Function: The Bass and Treble tone control features are active when this bit is enabled.
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6.17 Tone Control (Address 15h)
6 TREB2 5 TREB1 4 TREB0 3 BASS3 2 BASS2 1 BASS1 0 BASS0 7 TREB3
NOTE: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Treble Gain Level (TREB[3:0])
Default: 1000 dB (No Treble Gain)
Binary Code
0000
Gain Setting
+12.0 dB
***
0111 1000 1001
***
+1.5 dB 0 dB -1.5 dB
***
1111
***
-10.5 dB
Function: The level of the shelving treble gain filter is set by Treble Gain Level. The level can be adjusted in 1.5 dB increments from +12.0 to -10.5 dB.
Bass Gain Level (BASS[3:0])
Default: 1000 dB (No Bass Gain)
Binary Code
0000
Gain Setting
+12.0 dB
***
0111 1000 1001
***
+1.5 dB 0 dB -1.5 dB
***
1111
***
-10.5 dB
Function: The level of the shelving bass gain filter is set by Bass Gain Level. The level can be adjusted in 1.5 dB increments from +10.5 to -10.5 dB.
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6.18 AOUTx Volume Control: AOUTA (Address 16h) & AOUTB (Address 17h)
7 6 5 4 3 2 1 0 AOUTx_VOL7 AOUTx_VOL6 AOUTx_VOL5 AOUTx_VOL4 AOUTx_VOL3 AOUTx_VOL2 AOUTx_VOL1 AOUTx_VOL0
NOTE: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. AOUTX Volume Control (AOUTX_VOL[7:0])
Default = 00h
Binary Code 0001 1000 *** 0000 0000 1111 1111 1111 1110 *** 0011 0100 *** 0001 1001
Volume Setting +12.0 dB *** 0 dB -0.5 dB -1.0 dB *** -102 dB *** -102 dB
Function: The level of the analog outputs can be adjusted in 0.5 dB increments as dictated by the DAC Soft and Zero Cross bits (DACX_SZC[1:0]) from +12 to -102 dB. Levels are decoded as described in unsigned in the table above.
Note:
When the limiter is enabled the AOUT Volume is automatically controlled and should not be adjusted manually. Alternative volume control may be achieved using the PCMMIXx_VOL[6:0] bits.
6.19
ADC & PCM Channel Mixer (Address 18h)
6 PCMA0 5 PCMB1 4 PCMB0 3 ADCA1 2 ADCA0 1 ADCB1 0 ADCB0
7 PCMA1
NOTE: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Channel Mixer (PCMx[1:0] & ADCx[1:0])
Default: 00
PCMA[1:0] and/or ADCA[1:0]
00 01 10 11
AOUTA PCMB[1:0] and/or AOUTB ADCB[1:0]
L L+R ----------2 R 00 01 10 11 R L+R ----------2 L
Function: Implements mono mixes of the left and right channels as well as a left/right channel swap.
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6.20 Limiter Threshold SZC Disable (Address 19h)
6 MAX1 5 MAX0 4 CUSH2 3 CUSH1 2 CUSH0 1 LIM_SRDIS 0 LIM_ZCDIS 7 MAX2
NOTE: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Maximum Threshold (MAX[2:0])
Default: 000
MAX[2:0] Threshold Setting (dB)
000 001 010 011 101 101 110 111 0 -3 -6 -9 -12 -18 -24 -30
Function: Sets the maximum level, below fullscale, at which to limit and attenuate the output signal at the attack rate. Bass, Treble and digital gain settings that boost the signal beyond the maximum threshold may trigger an attack.
Cushion Threshold (CUSH[2:0])
Default: 000
CUSH[2:0] Threshold Setting (dB)
000 001 010 011 101 101 110 111 0 -3 -6 -9 -12 -18 -24 -30
Function: Sets a cushion level below fullscale. This setting is usually set slightly below the maximum (MAX[2:0]) threshold. The Limiter uses this cushion as a hysteresis point for the input signal as it maintains the signal below the maximum as well as below the cushion setting. This provides a more natural sound as the limiter attacks and releases.
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Limiter Soft Ramp Disable (LIM_SRDIS)
Default: 0 0 - Off 1 - On Function: Overrides the DAC_SZC setting. When this bit is set, the Limiter attack and release rate will not be dictated by the soft ramp setting. NOTE: This bit is ignored when the zero-cross function is enabled (i.e. when DAC_SZC[1:0] = `01'b or `11'b.)
Limiter Zero Cross Disable (LIM_ZCDIS)
Default: 0 0 - Off 1 - On Function: Overrides the DAC_SZC setting. When this bit is set, the Limiter attack & release rate will not be dictated by the zero cross setting.
6.21
Limiter Release Rate Register (Address 1Ah)
6 LIMIT_ALL 5 RRATE5 4 RRATE4 3 RRATE3 2 RRATE2 1 RRATE1 0 RRATE0
7 LIMIT_EN
NOTE: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Peak Detect and Limiter Enable (LIMIT_EN)
Default: 0 0 - Disabled 1 - Enabled Function: Limits the maximum signal amplitude to prevent clipping when this function is enabled. Peak Signal Limiting is performed by digital attenuation. NOTE: When the limiter is enabled the AOUT Volume is automatically controlled and should not be adjusted manually. Alternative volume control may be realized using the PCMMIXx_VOL[6:0] bits.
Peak Signal Limit All Channels (LIMIT_ALL)
Default: 1 0 - Individual Channel 1 - Both channel A & B Function: When set to 0, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on the specific channel indicating clipping. The other channels will not be affected. When set to 1, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on both channels in response to any single channel indicating clipping.
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Limiter RELEASE Rate (RRATE[5:0])
Default: 111111
Binary Code 000000 *** 111111
Release Time
Fastest Release
***
Slowest Release
Function: Sets the rate at which the limiter releases the digital attenuation from levels below the minimum setting in the limiter threshold register, and returns the analog output level to the AOUTx_VOL[7:0] setting. The limiter release rate is user selectable but is also a function of the sampling frequency, Fs, and the DAC_SZC setting unless the disable bit is enabled.
6.22
Limiter Attack Rate Register (Address 1Bh)
6 Reserved 5 ARATE5 4 ARATE4 3 ARATE3 2 ARATE2 1 ARATE1 0 ARATE0
7 Reserved
NOTE: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Limiter Attack Rate (ARATE[5:0])
Default: 000000
Binary Code 000000 *** 111111
Attack Time
Fastest Attack
***
Slowest Attack
Function: Sets the rate at which the limiter attenuates the analog output from levels above the maximum setting in the limiter threshold register. The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the DAC_SZC setting unless the disable bit is enabled.
6.23
ALC Enable & Attack Rate (Address 1Ch)
6 ALC_ENA 5 4 3 2 1 0 ALC_ARATE5 ALC_ARATE4 ALC_ARATE3 ALC_ARATE2 ALC_ARATE1 ALC_ARATE0
7 ALC_ENB
ALC Enable (ALC_ENX)
Default: 0 0 - Disabled 1 - Enabled Function: Enables automatic level control for ADC channel x.
Note:
When the ALC is enabled, the Attenuator and PGA volume is automatically controlled and should not be adjusted manually.
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ALC Attack Rate (ARATE[5:0])
Default: 000000
Binary Code 000000 *** 111111
Attack Time
Fastest Attack
***
Slowest Attack
Function: Sets the rate at which the ALC attenuates the analog input from levels above the maximum setting in the ALC threshold register. The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the SOFTx & ZCROSSx bit settings unless the disable bit for each function is enabled.
6.24
ALC Release Rate (Address 1Dh)
6 Reserved 5 4 3 2 1 0 ALC_RRATE5 ALC_RRATE4 ALC_RRATE3 ALC_RRATE2 ALC_RRATE1 ALC_RRATE0
7 Reserved
ALC Release Rate (RRATE[5:0])
Default: 111111
Binary Code 000000 *** 111111
Release Time
Fastest Release
***
Slowest Release
Function: Sets the rate at which the ALC releases the PGA & digital attenuation from levels below the minimum setting in the ALC threshold register, and returns the input level to the PGA_VOL[4:0] & ADCx_ATT[7:0] setting. The ALC release rate is user selectable but is also a function of the sampling frequency, Fs, and the SOFTx & ZCROSS bit settings unless the disable bit for each function is enabled.
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6.25 ALC Threshold (Address 1Eh)
6 MAX1 5 MAX0 4 MIN2 3 MIN1 2 MIN0 1 Reserved 0 Reserved 7 MAX2
Maximum Threshold (MAX[2:0])
Default: 000
MAX[2:0]
Threshold Setting (dB)
0 -3 -6 -9 -12 -18 -24 -30
000 001 010 011 100 101 110 111
Function: Sets the maximum level, relative to full-scale, at which to limit and attenuate the input signal at the attack rate.
Minimum Threshold (MIN[2:0])
Default: 000
MIN[2:0]
Threshold Setting (dB)
0 -3 -6 -9 -12 -18 -24 -30
000 001 010 011 100 101 110 111
Function: Sets the minimum level at which to disengage the ALC's attenuation or amplify the input signal at a rate set in the release rate register until levels again reach this minimum threshold. The ALC uses this minimum as a hysteresis point for the input signal as it maintains the signal below the maximum as well as below the minimum setting. This provides a more natural sound as the ALC attacks and releases.
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6.26 Noise Gate Configuration & Misc. (Address 1Fh)
6 NG_EN 5 NG_BOOST 4 THRESH2 3 THRESH1 2 THRESH0 1 NGDELAY1 0 NGDELAY0 7 NG_ALL
Noise Gate Channel Gang (NG_ALL)
Default: 0 0 - Disabled 1 - Enabled Function: Gangs the noise gate function for channel A and B. When enabled, both channels must fall below the threshold setting for the noise gate attenuation to take effect.
Noise Gate Enable (NG_EN)
Default: 0 0 - Disabled 1 - Enabled Function: Enables the noise gate. Maximum attenuation is relative to all gain settings applied.
Noise Gate Boost (NG_BOOST) and Threshold (THRESH[3:0])
Default: 000
THRESH[2:0]
000 001 010 011 100 101 110 111
Minimum Setting (NG_BOOST = `0'b) -64 dB -67 dB -70 dB -73 dB -76 dB -82 dB Reserved Reserved
Minimum Setting (NG_BOOST = `1'b) -34 dB -37 dB -40 dB -43 dB -46 dB -52 dB -58 dB -64 dB
Function: Sets the threshold level of the noise gate. Input signals below the threshold level will be attenuated to -96 dB. NG_BOOST = `1'b adds 30 dB to the threshold settings.
Noise Gate Delay Timing (NGDELAY[1:0])
Default: 00 00 - 50 ms 01 - 100 ms 10 - 150 ms 11 - 200 ms Function: Sets the delay time before the noise gate attacks. Noise gate attenuation is dictated by the SOFTx & ZCROSS bit settings unless the disable bit for each function is enabled.
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6.27 Status (Address 20h) (Read Only)
6 SP_CLKERR 5 SPEA_OVFL 4 SPEB_OVFL 3 2 PCMA_OVFL PCMB_OVFL 1 ADCA_OVFL 0 ADCB_OVFL 7 Reserved
For all bits in this register, a "1" means the associated error condition has occurred at least once since the register was last read. A"0" means the associated error condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0.
Serial Port Clock Error (SP_CLK Error)
Default: x Function: Indicates an invalid MCLK to LRCK ratio. See "Serial Port Clocking" on page 37 for valid clock ratios.
Note:
On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes.
Signal Processing Engine Overflow (MIXX_OVFL)
Default: x Function: Indicates a digital overflow condition within the data path after the signal processing engine.
PCMX Overflow (PCMX_OVFL)
Default: x Function: Indicates a digital overflow condition within the data path of the PCM mix.
ADC Overflow (ADCX_OVFL)
Default = x Function: Indicates that there is an over-range condition anywhere in the CS42L51 ADC signal path of each of the associated ADC's.
6.28
Charge Pump Frequency (Address 21h)
3 Reserved 2 Reserved 1 Reserved 0 Reserved
7 6 5 4 CHRG_FREQ CHRG_FREQ CHRG_FREQ CHRG_FREQ 3 2 1 0
Charge Pump Frequency (CHRG_FREQ[3:0])
Default: 0101
N 0 ... 15
CHRG_FREQ[3:0] 0000 ... 1111
Frequency
64xFs ---------------N+2
Function: Alters the clocking frequency of the charge pump in 1/(N+2) fractions of the DAC oversampling rate, 128Fs, should the switching frequency interfere with other system frequencies such as those in the AM radio band.
Note:
Distortion performance may be affected.
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CS42L51 7. ANALOG PERFORMANCE PLOTS
7.1 Headphone THD+N versus Output Power Plots
Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48 kHz. Plots were taken from the CDB42L51 using an Audio Precision analyzer.
-10
G = 0.6047
-15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 0
VA_HP = VA = 1.8 V
G = 0.7099 G = 0.8399 G = 1.0000 G = 1.1430 Legend
d B r A
NOTE: Graph shows the output power per channel (i.e. Output Power = 23 mW into single 16 and 46 mW into stereo 16 with THD+N = 75 dB).
10m
20m
30m
40m W
50m
60m
70m
80m
Figure 28. THD+N vs. Ouput Power per Channel at 1.8 V (16 load)
-10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 0
G = 0.6047
VA_HP = VA = 2.5 V
G = 0.7099 G = 0.8399 G = 1.0000 G = 1.1430 Legend
d B r A
NOTE: Graph shows the output power per channel (i.e. Output Power = 44 mW into single 16 and 88 mW into stereo 16 with THD+N = 75 dB).
10m
20m
30m
40m W
50m
60m
70m
80m
Figure 29. THD+N vs. Ouput Power per Channel at 2.5 V (16 load)
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G = 0.6047 G = 0.7099 G = 0.8399 G = 1.0000
-40 -45
VA_HP = VA = 1.8
-20 -30
-35
G = 1.1430 Legend
-50
-55 d B r A -65
-60
-70
-75
NOTE: Graph shows the output power per channel (i.e. Output Power = 22 mW into single 32 and 44 mW into stereo 32 with THD+N = 75 dB).
-80
-85
-90
-95
-100 0
6m
12m
18m
24m
30m W
36m
42m
48m
54m
60m
Figure 30. THD+N vs. Ouput Power per Channel at 1.8 V (32 load)
-20
VA_HP = VA = 2.5 V
-25 -30
G = 0.6047 G = 0.7099 G = 0.8399
-35
G = 1.0000
-40 -45
G = 1.1430 Legend
-50
-55 d B r A -65
-60
-70
-75
-80
NOTE: Graph shows the output power per channel (i.e. Output Power = 42 mW into single 32 and 84 mW into stereo 32 with THD+N = 75 dB).
-85
-90
-95
-100 0
5m
10m
15m
20m
25m
30m W
35m
40m
45m
50m
55m
60m
Figure 31. THD+N vs. Ouput Power per Channel at 2.5 V (32 load)
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7.2 ADC_FILT+ Capacitor Effects on THD+N
The value of the capacitor on the ADC_FILT+ pin, 16, affects the low frequency total harmonic distortion + noise (THD+N) performance of the ADC. Larger capacitor values yield significant improvement in THD+N at low frequencies. Figure 32 shows the THD+N versus frequency for the ADC analog input. Plots were taken from the CDB42L51 using an Audio Precision analyzer.
-60
-64
1 F 10 F 22 F Legend - Capacitor Value on ADC_FILT+
-68
-72
-76 d B F S
-80
-84
-88
-92
-96
-100 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 32. ADC THD+N vs. Frequency w/Capacitor Effects
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CS42L51 8. EXAMPLE SYSTEM CLOCK FREQUENCIES
8.1 Auto Detect Enabled
Sample Rate LRCK (kHz)
8 11.025 12
1024x
8.1920 11.2896 12.2880
MCLK (MHz) 1536x 2048x*
12.2880 16.9344 18.4320 16.3840 22.5792 24.5760
3072x*
24.5760 33.8688 36.8640
Sample Rate LRCK (kHz)
16 22.05 24
512x
8.1920 11.2896 12.2880
MCLK (MHz) 768x 1024x*
12.2880 16.9344 18.4320 16.3840 22.5792 24.5760
1536x*
24.5760 33.8688 36.8640
Sample Rate LRCK (kHz)
32 44.1 48
256x
8.1920 11.2896 12.2880
MCLK (MHz) 384x 512x*
12.2880 16.9344 18.4320 16.3840 22.5792 24.5760
768x*
24.5760 33.8688 36.8640
Sample Rate LRCK (kHz)
64 88.2 96
128x
8.1920 11.2896 12.2880
192x
MCLK (MHz) 256x*
16.3840 22.5792 24.5760
384x*
24.5760 33.8688 36.8640
12.2880 16.9344 18.4320
*The "MCLKDIV2" pin 4 must be set HI.
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8.2 Auto Detect Disabled
Sample Rate LRCK (kHz)
8 11.025 12
512x
6.1440
768x
6.1440 8.4672 9.2160
MCLK (MHz) 1024x 1536x
8.1920 11.2896 12.2880 12.2880 16.9344 18.4320
2048x
16.3840 22.5792 24.5760
3072x
24.5760 33.8688 36.8640
Sample Rate LRCK (kHz)
16 22.05 24
256x
6.1440
384x
6.1440 8.4672 9.2160
512x
8.1920 11.2896 12.2880
MCLK (MHz) 768x
12.2880 16.9344 18.4320
1024x
16.3840 22.5792 24.5760
1536x
24.5760 33.8688 36.8640
Sample Rate LRCK (kHz)
32 44.1 48
256x
8.1920 11.2896 12.2880
384x
12.2880 16.9344 18.4320
MCLK (MHz) 512x
16.3840 22.5792 24.5760
768x
24.5760 33.8688 36.8640
Sample Rate LRCK (kHz)
64 88.2 96
128x
8.1920 11.2896 12.2880
MCLK (MHz) 192x 256x
12.2880 16.9344 18.4320 16.3840 22.5792 24.5760
384x
24.5760 33.8688 36.8640
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CS42L51 9. PCB LAYOUT CONSIDERATIONS
9.1 Power Supply, Grounding
As with any high resolution converter, the CS42L51 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 on page 10 shows the recommended power arrangements, with VA and VA_HP connected to clean supplies. VD, which powers the digital circuitry, may be run from the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead. In this case, no additional devices should be powered from VD. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS42L51 as possible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same side of the board as the CS42L51 to minimize inductance effects. All signals, especially clocks, should be kept away from the DAC_FILT+/ADC_FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The DAC_FILT+/ADC_FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from DAC_FILT+/ADC_FILT+ and AGND. The CDB42L51 evaluation board demonstrates the optimum layout and power supply arrangements.
9.2
QFN Thermal Pad
The CS42L51 is available in a compact QFN package. The under side of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers. In split ground systems, it is recommended that this thermal pad be connected to AGND for best performance. The CS42L51 evaluation board demonstrates the optimum thermal pad and via configuration.
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CS42L51 10.ADC & DAC DIGITAL FILTERS
0.3 0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (normalized to Fs)
0 -10 -20 Amplitude dB -30 -40 -50 -60 -70 -80 -90 -100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (normalized to Fs)
Amplitude dB
Figure 33. ADC Passband Ripple
Figure 34. ADC Stopband Rejection
0 -10 -20 Amplitude dB Amplitude dB -30 -40 -50 -60 -70 -80 -90 -100 0.4 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 Frequency (normalized to Fs)
0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
Frequency (normalized to Fs)
Figure 35. ADC Transition Band
Figure 36. ADC Transition Band (Detail)
Figure 35. DAC Passband Ripple
Figure 36. DAC Stopband
Figure 35. DAC Transition Band
Figure 36. DAC Transition Band (Detail)
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CS42L51 11.PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channel pairs. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channel pairs. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
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CS42L51 12.PACKAGE DIMENSIONS
32L QFN (5 X 5 mm BODY) PACKAGE DRAWING
D b e Pin #1 Corner
Pin #1 Corner
E
E2
A1 A Top View Side View
L
D2
Bottom View
DIM A A1 b D D2 E E2 e L
MIN -0.0000 0.0071
0.1280 0.1280 0.0118
INCHES NOM --0.0091 0.1969 BSC 0.1299 0.1969 BSC 0.1299 0.0197 BSC 0.0157
MAX 0.0394 0.0020 0.0110
0.1319 0.1319 0.0197
MIN -0.00 0.18
3.25 3.25 0.30
MILLIMETERS NOM --0.23 5.00 BSC 3.30 5.00 BSC 3.30 0.50 BSC 0.40
NOTE MAX 1.00 0.05 0.28
3.35 3.35 0.50 1 1 1,2 1 1 1 1 1 1
JEDEC #: MO-220 Controlling Dimension is Millimeters. 1. Dimensioning and tolerance per ASME Y 14.5M-1995. 2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip.
THERMAL CHARACTERISTICS
Parameter
Junction to Ambient Thermal Impedance 2 Layer Board 4 Layer Board
Symbol
JA
Min
-
Typ
52 38
Max
-
Units
C/Watt
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CS42L51 13.ORDERING INFORMATION
Product
CS42L51
Description
Low-Power Stereo CODEC w/HP Amp for Portable Apps CS42L51 Evaluation Board CS42L51 Reference Design
Package Pb-Free
32L-QFN Yes
Grade
Temp Range
Container
Order #
Commercial -10 to +70 C Automotive No No -40 to +85 C -
Rail CS42L51-CNZ Tape & Reel CS42L51-CNZR Rail CS42L51-DNZ Tape & Reel CS42L51-DNZR CDB42L51 CRD42L51
CDB42L51 CRD42L51
14.REFERENCES
1. Cirrus Logic, Audio Quality Measurement Specification, Version 1.0, 1997. http://www.cirrus.com/products/papers/meas/meas.html 2. Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version 6.0, February 1998. 3. Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Converter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Convention of the Audio Engineering Society, September 1997. 4. Cirrus Logic, A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio, by D.R. Welland, B.P. Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th Convention of the Audio Engineering Society, November 1988. 5. Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 6. Cirrus Logic, An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Application Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 7. Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters, by Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992. 8. Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 9. Philips Semiconductor, The IC-Bus Specification: Version 2.1, January 2000. http://www.semiconductors.philips.com
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CS42L51 15.REVISION HISTORY
Rev.
A1 A2
Date
May 2005 Initial Release subject to legal notice.
Changes
September 2005 Renamed pin 14, FILT1+, to DAC_FILT+ and pin 16, FILT2+, to ADC_FILT+. Added 1.5 F capacitor recommendation to figure "Typical Connection Diagram (Software Mode)" on page 10. Removed the 0.1F capacitors from pins DAC_FILT+, ADC_FILT+ and VQ on the figures "Typical Connection Diagram (Software Mode)" on page 10 and "Typical Connection Diagram (Hardware Mode)" on page 11. Added DAC Isolation specification to "Analog Input Characteristics (Commercial - CNZ)" on page 13 and "Analog Input Characteristics (Automotive - DNZ)" on page 14. Corrected specification table "Headphone Output Power Characteristics" on page 19. Removed td timing specification from table in section "Switching Specifications - Serial Port" on page 20. Added ts(SDO-SK) and th(SK-SDO) timing specification to table in section "Switching Specifications Serial Port" on page 20. Adjusted timing specifications ts(SD-SK) from 0 ns to 20 ns and th from 50 ns to 20 ns in table in section "Switching Specifications - Serial Port" on page 20. Added MIC Bias PSRR specification to "DC Electrical Characteristics" on page 24. Adjusted specification table "Power Consumption" on page 25. Removed QSM clock ratios 128, 192, 256, 384 and HSM ratios 128, 192 from Table 3 on page 37. Modified Digital Mix description in section "Digital Mix (DIGMIX)" on page 50. Corrected DAC Zero Cross timeout period in section "Zero Cross" on page 56. Adjusted BEEP off time settings in section "Beep Off Time (OFFTIME[2:0])" on page 61. Modified BEEP description in section "Beep (BEEP)" on page 62. Adjusted the minimum settings for the "Noise Gate Boost (NG_BOOST) and Threshold (THRESH[3:0])" on page 70. Swapped bits PCMA_OVFL w/PCMB_OVFL and ADCA_OVFL w/ADCB_OVFL in register "Status (Address 20h) (Read Only)" on page 71. Corrected Charge Pump Frequency setting in section "Charge Pump Frequency (CHRG_FREQ[3:0])" on page 71. Added sections "Headphone THD+N versus Output Power Plots" on page 72 and "ADC_FILT+ Capacitor Effects on THD+N" on page 74.
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CS42L51
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc.
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